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21 search results found

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

Sv Tests ⭐ 257

Test suite designed to check compliance with the SystemVerilog standard.

Hdl_checker ⭐ 136

Repurposing existing HDL tools to help writing better code

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Brianhg Ddr3 Controller ⭐ 34

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

My Verilog Examples ⭐ 22

A place to keep my synthesizable verilog examples.

Virtio implementation in SystemVerilog

Fpga Ethernet Udp ⭐ 17

An HDL design for sending data over Ethernet

Awesome Fpga List ⭐ 12

A collection of some awesome public FPGA projects.

Svlogger ⭐ 11

SystemVerilog Logger

An HDL package manager.

A Tcl-Library for scripted HDL generation

Blockwork ⭐ 9

An opinionated build environment for EDA projects

Hardware description language that tries not to suck

Python Frontend For VHDL And Verilog

Linter Veriloghdl ⭐ 6

Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.

An open source, parameterized SystemVerilog digital hardware IP library

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

Sphinx Verilog Domain ⭐ 5

Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.

Open FPGA Debug core

Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster

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1-21 of 21 search results

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