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Search results for python hdl

30 search results found

Amaranth ⭐ 1,346

A modern hardware definition language and toolchain based on Python

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

A huge VHDL library for FPGA development

F4pga Arch Defs ⭐ 245

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Reviews ⭐ 242

Reviewing some online CS courses I took

Hdl_checker ⭐ 136

Repurposing existing HDL tools to help writing better code

Cocotb Coverage ⭐ 94

Functional Coverage and Constrained Randomization Extensions for Cocotb

HW Design: A Functional Approach

PCB Design Language: A programming way to design schematics.

Symbolator ⭐ 73

HDL symbol generator

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

Sphinxcontrib Hdl Diagrams ⭐ 43

Sphinx Extension which generates various types of diagrams from Verilog code.

Cross EDA Abstraction and Automation

Icebreaker Amaranth Examples ⭐ 23

This repository contains iCEBreaker examples for Amaranth HDL.

Migen Axi ⭐ 22

AXI support for Migen/MiSoC

Hacktoberfest ⭐ 12

This Repository invites freelancer friendly neighbourhood developers to contribute to open source .

Study Materials ⭐ 12

Fpga Mandelbrot ⭐ 11

FPGA mandelbrot accelerator via high speed/super speed USB

Fpga_hw_sim_fwk_2 ⭐ 10

FPGA Hardware Simulation Framework

Hdlgen Chatgpt ⭐ 9

HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project

Blockwork ⭐ 9

An opinionated build environment for EDA projects

Fpga_hw_sim_fwk ⭐ 8

FPGA Hardware Simulation Framework

Complex_multiplier ⭐ 8

HDL code for a complex multiplier with AXI stream Interface

HDL code for a DDS (direct digital synthesizer) with AXI stream interface

Hardware Design/Visualization/Simulation/RTLGeneration Framework

HDL code for a complex multiplier with AXI stream interface

Python Frontend For VHDL And Verilog

Sphinx Verilog Domain ⭐ 5

Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.

An experimental package manager and development tool for Hardware Description Languages (HDL).

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