Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Simplevout | 112 | 5 years ago | Verilog | |||||||
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals | ||||||||||
Verilog Uart | 56 | 8 months ago | gpl-3.0 | Verilog | ||||||
3 modules: UART receiver, UART transmitter, UART to AXI4 master. 3个模块:UART接收器、UART发送器、UART转AXI4交互式调试器 | ||||||||||
Collection Ipxs | 33 | 6 years ago | gpl-2.0 | Verilog | ||||||
Icestudio Pixel Stream collection | ||||||||||
Vcd | 32 | 3 | 3 months ago | 27 | March 12, 2023 | 16 | mit | JavaScript | ||
Value Change Dump (VCD) parser | ||||||||||
Fpga Sdrlib | 13 | 11 years ago | mit | Python | ||||||
Verilog modules for software-defined radio. | ||||||||||
Bladerf Dvbs2 | 9 | 6 years ago | Verilog | |||||||
16-APSK DVB-S2 Transmitter for BladeRF | ||||||||||
Net2axis | 9 | 5 years ago | isc | Verilog | ||||||
Verilog network module. Models network traffic from pcap to AXI-Stream | ||||||||||
Complex_multiplier | 8 | a year ago | Python | |||||||
HDL code for a complex multiplier with AXI stream Interface | ||||||||||
Verilog Ft245 | 8 | 6 years ago | mit | Python | ||||||
Verilog FT245 to AXI stream interface | ||||||||||
Otl Icoboard Pmodoledrgb Demo | 6 | 6 years ago | bsd-3-clause | Verilog | ||||||
A demo project that uses the IcoBoard to render graphics on a PmodOLEDrgb display |