Simplevout
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Bitwise | 4,582 | 5 years ago | 17 | other | C | |||||
| Bitwise is an educational project where we create the software/hardware stack for a computer from scratch. | ||||||||||
| Hlslib | 236 | a year ago | 5 | bsd-3-clause | C++ | |||||
| A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life. | ||||||||||
| Simplevout | 112 | 6 years ago | Verilog | |||||||
| A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals | ||||||||||
| Fastvdma | 92 | 5 months ago | 5 | apache-2.0 | Scala | |||||
| Antmicro's fast, vendor-neutral DMA IP in Chisel | ||||||||||
| Prjtang | 79 | a year ago | isc | C++ | ||||||
| Documenting the Anlogic FPGA bit-stream format. | ||||||||||
| Verilog Uart | 56 | 9 months ago | gpl-3.0 | Verilog | ||||||
| 3 modules: UART receiver, UART transmitter, UART to AXI4 master. 3个模块：UART接收器、UART发送器、UART转AXI4交互式调试器 | ||||||||||
| Stream | 24 | 9 years ago | VHDL | |||||||
| FPGA development platform for high-performance RF and digital design | ||||||||||
| Fpga_cores | 21 | a year ago | other | VHDL | ||||||
| Hls Cnn | 19 | 6 months ago | mit | C | ||||||
| High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition. | ||||||||||
| J1eforth | 14 | 9 years ago | 1 | Forth | ||||||
| eForth for the j1 simulator and actual J1 FPGAs | ||||||||||
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