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Search results for verilog hdl

67 search results found

HDL libraries and projects

Metroboy ⭐ 1,089

A repository of gate-level simulators and tools for the original Game Boy.

Awesome Hdl ⭐ 830

Hardware Description Languages

Bsv_tutorial_cn ⭐ 381

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

Sv Tests ⭐ 257

Test suite designed to check compliance with the SystemVerilog standard.

F4pga Arch Defs ⭐ 245

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

An HDL embedded in Rust.

Async_fifo ⭐ 173

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Fomu Workshop ⭐ 148

Support files for participating in a Fomu workshop

A C++ to Verilog translation tool with some basic guarantees that your code will work.

Revengineered ancient PDP-11 CPUs, originals and clones

Hdl_checker ⭐ 136

Repurposing existing HDL tools to help writing better code

Open5g_phy ⭐ 135

A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Symbolator ⭐ 73

HDL symbol generator

A reimplementation of a tiny stack CPU

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

Hdl Tools ⭐ 60

Facilitates building open source tools for working with hardware description languages (HDLs)

Sol-1: A CPU/Computer System made from 74 series logic.

Web-based HDL diagramming tool

Sphinxcontrib Hdl Diagrams ⭐ 43

Sphinx Extension which generates various types of diagrams from Verilog code.

Brianhg Ddr3 Controller ⭐ 34

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

Virtual development board for HDL design

Gateware Ts ⭐ 33

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Value Change Dump (VCD) parser

Speech256 ⭐ 31

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

Collection of projects for various FPGA development boards

Cross EDA Abstraction and Automation

Ophidian ⭐ 29

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

Fpu Wrappers ⭐ 24

Wrappers for open source FPU hardware implementations.

🔁 elastic circuit toolchain

My Verilog Examples ⭐ 22

A place to keep my synthesizable verilog examples.

Verilog Doc ⭐ 22

KISCV, a KISS principle riscv32i CPU

Virtio implementation in SystemVerilog

Picoblaze Library ⭐ 18

The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).

Verilog Starter Tutorials ⭐ 17

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

Study Materials ⭐ 12

Bugu Computer ⭐ 12

💻 build own computer by fpga.

Awesome Fpga List ⭐ 12

A collection of some awesome public FPGA projects.

Arcade Digdug ⭐ 11

Namco Dig Dug Compatible Gateware IP Core

Svlogger ⭐ 11

SystemVerilog Logger

An HDL package manager.

Discretize ⭐ 10

A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad

HTML & Js based VCD viewer

A Tcl-Library for scripted HDL generation

Hdlgen Chatgpt ⭐ 9

HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project

Complex_multiplier ⭐ 8

HDL code for a complex multiplier with AXI stream Interface

Mastering Fpgasic Book ⭐ 8

📖 Mastering FPGASIC Book

HDL code for a DDS (direct digital synthesizer) with AXI stream interface

100daysof_rtl ⭐ 7

The Repository contains the code of various Digital Circuits

Hardware description language that tries not to suck

Wrapped_rgb_mixer ⭐ 7

Demo project for the Zero to ASIC Course.

Kintex 7 Imx291 Verilog ⭐ 7

Kintex-7-IMX291-Verilog

Hardware Design/Visualization/Simulation/RTLGeneration Framework

HDL code for a complex multiplier with AXI stream interface

Frequency_counter ⭐ 6

Project 2.2 Frequency counter

Linter Veriloghdl ⭐ 6

Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.

Applied_digital_logic_exercises_using_fpgas ⭐ 6

Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.

Python Frontend For VHDL And Verilog

An open source, parameterized SystemVerilog digital hardware IP library

Describing RTL circuit in Ruby

Sphinx Verilog Domain ⭐ 5

Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.

Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster

An experimental package manager and development tool for Hardware Description Languages (HDL).

Gost 28147 89 ⭐ 5

Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher

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