Project Name	Stars	Most Recent Commit	Open Issues	License	Language
Vboard	34	a year ago			VHDL
Virtual development board for HDL design
Tonic	20	3 years ago	1	bsd-3-clause	Verilog
A Programmable Hardware Architecture for Network Transport Logic
Mesabusprotocol	13	7 years ago			Verilog
Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces
Bladerf Dvbs2	9	6 years ago			Verilog
16-APSK DVB-S2 Transmitter for BladeRF

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Vboard ⭐ 34

Virtual development board for HDL design

most recent commit a year ago

Tonic ⭐ 20

A Programmable Hardware Architecture for Network Transport Logic

most recent commit 3 years ago

Mesabusprotocol ⭐ 13

Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces

most recent commit 7 years ago

Bladerf Dvbs2 ⭐ 9

16-APSK DVB-S2 Transmitter for BladeRF

most recent commit 6 years ago

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