Awesome Open Source
Search
Programming Languages
Languages
All Categories
Categories
About
Search results for clock verilog
clock
x
verilog
x
65 search results found
Darkriscv
⭐
1,795
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Silice
⭐
1,199
Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.
Risc V Single Cycle Cpu
⭐
380
A RISC-V 32bit single-cycle CPU written in Logisim
Openofdm
⭐
251
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
Dblclockfft
⭐
195
A configurable C++ generator of pipelined Verilog FFT cores
Autofpga
⭐
153
A utility for Composing FPGA designs from Peripherals
Usbcorev
⭐
146
A full-speed device-side USB peripheral core written in Verilog.
Dspfilters
⭐
119
A collection of demonstration digital filters
Icestation 32
⭐
107
Compact FPGA game console
Displayport_verilog
⭐
88
A Verilog implementation of DisplayPort protocol for FPGAs
Xilinx Serial Miner
⭐
75
Bitcoin miner for Xilinx FPGAs
Symbolator
⭐
73
HDL symbol generator
Core_ddr3_controller
⭐
69
A DDR3 memory controller in Verilog for various FPGAs
Ponylink
⭐
63
A single-wire bi-directional chip-to-chip interface for FPGAs
Verilog_fixed_point_math_library
⭐
44
Fixed Point Math Library for Verilog
Basic Simd Processor Verilog Tutorial
⭐
41
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
Cxxrtl_eval
⭐
40
Experiments with Yosys cxxrtl backend
Hyperram
⭐
39
Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
Jt49
⭐
39
Verilog clone of YM2149
Vga Clock
⭐
33
Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
Sdram Controller
⭐
27
Generic FPGA SDRAM controller, originally made for AS4C4M16SA
Icebreaker Candy
⭐
24
Eye candy from an iCEBreaker FPGA and a 64×64 LED panel
Ov7670 Verilog
⭐
23
Verilog modules required to get the OV7670 camera working
Uhd Fairwaves
⭐
22
Fairwaves version of the UHD drivers, tweaked to support Fairwaves UmTRX.
Fpga Virtual Graf
⭐
21
Aoocs
⭐
20
The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is not related in any way with Minimig - it is a new and independent Amiga OCS implementation.
Osdvu
⭐
19
Rtcclock
⭐
19
A Real Time Clock core for FPGA's
Fifo
⭐
18
Generic FIFO implementation with optional FWFT
Fpga_gameboy_watch
⭐
17
Full gameboy and gameboy color Verilog Implenentation
Async Karin
⭐
17
Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.
Verifla
⭐
16
Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm
Hardcaml_of_verilog
⭐
15
Convert Verilog to a Hardcaml design
Second_order_sigma_delta_dac
⭐
15
A comparison of 1st and 2nd order sigma delta DAC for FPGA
Midi Stepper Synth V2
⭐
15
Virginia Tech AMP Lab Version of the MIDI Stepper Synth. Uses FPGA and 32 Stepper Motors.
Memtest_mister
⭐
14
Upduino Mecrisp Ice 15kb
⭐
14
Mecrisp-Ice Forth running on 16bit j1a processor (iCE40UP5k based UPduino board) with full 15kB of bram and 48bit Floating Point Library.
Flappybird
⭐
12
Flappy Bird on Verilog
Jt6295
⭐
12
ADPCM decoder compatible with OKI 6295
Vcdvis
⭐
11
VCD visualizer: view your waveforms in ASCII format, or export them to TikZ figures.
Systemc Tutorial
⭐
11
Brief SystemC getting started tutorial
Ft245_interface
⭐
10
Verilog module to communicate with the FT245 interface of an FTDI FT2232H
Nmigen Examples
⭐
10
I want to learn [n]Migen.
Fpga Bicubic Interpolation
⭐
10
use Verilog HDL implemente bicubic interpolation in FPGA
Quickspi
⭐
9
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
Pulse Width Modulation Ip
⭐
8
A PWM Module IP core written in Verilog, along with a firmware driver (developed for the Zynq-7000 Programmable SoC)
Hardcaml Yosys
⭐
8
[DEPRECATED] Import verilog designs into hardcaml using yosys
Spi
⭐
7
spi memory controller
Verilog Spi
⭐
7
This is a SPI Master Module Written in Verilog
Ice40_power
⭐
7
Power analysis of the ICE40UP5K-SG48 devices
Core_spiflash
⭐
7
SPI-Flash XIP Interface (Verilog)
Wbspi
⭐
7
A collection of SPI related cores
Verilog Spi Master
⭐
7
A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen
Asynchronous Fifo
⭐
7
Asynchronous fifo in verilog
Pin Assignment For De10 Standard
⭐
6
FPGA实验用DE10-Standard开发板引脚表
Usrp1_openbts
⭐
6
Altera Quartus Project for OpenBTS USRP1 Cyclone FPGA bitstream
Mist Modules
⭐
6
Common modules for cores
Ie12
⭐
6
A (very) minimal web browser for FPGAs implemented in Verilog
Verilog Buildingblocks
⭐
6
Library of generic verilog buildingblocks
Double_fpu
⭐
5
double_fpu_verilog
Ahb_lite_sdram
⭐
5
SDRAM controller for MIPSfpga+ system
Fpdpga
⭐
5
FPGA implementations of the PDP-6 and PDP-10
Core_audio
⭐
5
Audio controller (I2S, SPDIF, DAC)
Fpga Dvid Ice
⭐
5
Sub 25 Ns Nasdaq Itch Fpga Parser
⭐
5
Related Searches
Verilog Fpga (1,343)
Javascript Clock (1,022)
C Plus Plus Clock (764)
C Clock (648)
Python Clock (589)
Time Clock (567)
Arduino Clock (522)
Java Clock (390)
Cpu Verilog (330)
Led Clock (302)
1-65 of 65 search results
Privacy
|
About
|
Terms
|
Follow Us On Twitter
Copyright 2018-2024 Awesome Open Source. All rights reserved.