Mist Modules
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Darkriscv | 1,795 | 5 months ago | 9 | bsd-3-clause | Verilog | |||||
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! | ||||||||||
| Silice | 1,199 | 3 months ago | 73 | other | C++ | |||||
| Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures. | ||||||||||
| Risc V Single Cycle Cpu | 380 | a year ago | mit | Verilog | ||||||
| A RISC-V 32bit single-cycle CPU written in Logisim | ||||||||||
| Openofdm | 251 | a year ago | 8 | apache-2.0 | Verilog | |||||
| Sythesizable, modular Verilog implementation of 802.11 OFDM decoder. | ||||||||||
| Dblclockfft | 195 | 4 months ago | 3 | C++ | ||||||
| A configurable C++ generator of pipelined Verilog FFT cores | ||||||||||
| Autofpga | 153 | 4 months ago | 2 | gpl-3.0 | C++ | |||||
| A utility for Composing FPGA designs from Peripherals | ||||||||||
| Usbcorev | 146 | 2 years ago | 2 | other | Verilog | |||||
| A full-speed device-side USB peripheral core written in Verilog. | ||||||||||
| Dspfilters | 119 | 4 months ago | 1 | Verilog | ||||||
| A collection of demonstration digital filters | ||||||||||
| Icestation 32 | 107 | 3 years ago | 2 | mit | Verilog | |||||
| Compact FPGA game console | ||||||||||
| Displayport_verilog | 88 | 5 years ago | 1 | mit | Verilog | |||||
| A Verilog implementation of DisplayPort protocol for FPGAs | ||||||||||
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