Hdl Tools

Facilitates building open source tools for working with hardware description languages (HDLs)
Alternatives To Hdl Tools
Project NameStarsDownloadsRepos Using ThisPackages Using ThisMost Recent CommitTotal ReleasesLatest ReleaseOpen IssuesLicenseLanguage
Chisel3,685911 days ago59April 14, 2023397apache-2.0Scala
Chisel: A Modern Hardware Design Language
Verilator1,93413 months ago8October 04, 2022304lgpl-3.0C++
Verilator open-source SystemVerilog simulator and lint system
Darkriscv1,795
5 months ago9bsd-3-clauseVerilog
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Spinalhdl1,45143 months ago140November 01, 2023106otherScala
Scala based HDL
Hw1,254
2 years ago193otherVerilog
RTL, Cmodel, and testbench for NVDLA
Openlane1,148
a month ago138apache-2.0Python
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Openroad1,102
3 months ago282bsd-3-clauseVerilog
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Scr1688
7 months ago3otherSystemVerilog
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Openwifi Hw560
4 months ago5agpl-3.0Verilog
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Riscv_vhdl552
4 months ago2apache-2.0Verilog
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
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