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65 search results found
Amaranth
⭐
1,346
A modern hardware definition language and toolchain based on Python
Hdl
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1,299
HDL libraries and projects
Nmigen
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589
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
Bsv_tutorial_cn
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381
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开
Plutosdr Fw
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262
PlutoSDR Firmware
Surf
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259
A huge VHDL library for FPGA development
Bladerf Wiphy
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255
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
F4pga Arch Defs
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245
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Tensil
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218
Open source machine learning accelerators
Livehd
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192
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
Async_fifo
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173
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Kactus2dev
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168
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
Fomu Workshop
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148
Support files for participating in a Fomu workshop
Metron
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143
A C++ to Verilog translation tool with some basic guarantees that your code will work.
Open5g_phy
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135
A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog
Logic
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121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Pygears
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93
HW Design: A Functional Approach
J1sc
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72
A reimplementation of a tiny stack CPU
Dfiant
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56
DFiant: A Dataflow Hardware Descripition Language
Hdelk
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50
Web-based HDL diagramming tool
M2k Fw
⭐
49
M2k firmware for the ADALM-2000 Active Learning Module
Hdlab Fpga Development Board
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43
Open source FPGA development platform
Sphinxcontrib Hdl Diagrams
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43
Sphinx Extension which generates various types of diagrams from Verilog code.
Brianhg Ddr3 Controller
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34
DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
Gateware Ts
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33
Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools
Speech256
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31
An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.
Fpga
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30
Collection of projects for various FPGA development boards
Xeda
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30
Cross EDA Abstraction and Automation
Icebreaker Amaranth Examples
⭐
23
This repository contains iCEBreaker examples for Amaranth HDL.
My Verilog Examples
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22
A place to keep my synthesizable verilog examples.
Hdx
⭐
21
[mirror] HDL development environment on Nix.
Hls Cnn
⭐
19
High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
Picoblaze Library
⭐
18
The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).
Virtio
⭐
18
Virtio implementation in SystemVerilog
Fpga Ethernet Udp
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17
An HDL design for sending data over Ethernet
Shdl6800
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17
shdl6800: A 6800 processor written in SpinalHDL
Tcl_for_fpga
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15
TCL scripts for FPGA (Xilinx)
Icyradio
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15
Over-engineered SDR development board
Fsva
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15
FuseSoc Verification Automation
Bugu Computer
⭐
12
💻 build own computer by fpga.
Study Materials
⭐
12
Awesome Fpga List
⭐
12
A collection of some awesome public FPGA projects.
Fpga Mandelbrot
⭐
11
FPGA mandelbrot accelerator via high speed/super speed USB
Arcade Digdug
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11
Namco Dig Dug Compatible Gateware IP Core
Svlogger
⭐
11
SystemVerilog Logger
Fpga_hw_sim_fwk_2
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10
FPGA Hardware Simulation Framework
Hdlgen Chatgpt
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9
HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project
J1 Forth
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9
Forth for the J1-CPU
Freesrp_gw
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9
The FPGA design for the FreeSRP's Artix 7 FPGA
Spinalhdl Template
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8
Mill template for beginning your SpinalHDL project
Complex_multiplier
⭐
8
HDL code for a complex multiplier with AXI stream Interface
Fpga_hw_sim_fwk
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8
FPGA Hardware Simulation Framework
Mastering Fpgasic Book
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8
📖 Mastering FPGASIC Book
Dds
⭐
8
HDL code for a DDS (direct digital synthesizer) with AXI stream interface
Phi
⭐
7
Hardware description language that tries not to suck
Kintex 7 Imx291 Verilog
⭐
7
Kintex-7-IMX291-Verilog
Py4hw
⭐
7
Hardware Design/Visualization/Simulation/RTLGeneration Framework
Libsv
⭐
6
An open source, parameterized SystemVerilog digital hardware IP library
Apogeorv
⭐
6
A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
Applied_digital_logic_exercises_using_fpgas
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6
Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.
Tinyuart
⭐
5
Lightweight UART core in VHDL
Torii Hdl
⭐
5
A modern hardware definition language and toolchain based on Python
Ofd
⭐
5
Open FPGA Debug core
Legohdl
⭐
5
An experimental package manager and development tool for Hardware Description Languages (HDL).
Gost 28147 89
⭐
5
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
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