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Search results for cpu fpga
cpu
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fpga
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136 search results found
Litex
⭐
2,546
Build your hardware, easily!
Vexriscv
⭐
2,135
A FPGA friendly 32 bit RISC-V CPU implementation
Cva6
⭐
2,042
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Darkriscv
⭐
1,795
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
E200_opensource
⭐
1,688
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
Neorv32
⭐
1,337
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Zipcpu
⭐
1,139
A small, light weight, RISC CPU soft core
Tornadovm
⭐
1,054
TornadoVM: A practical and efficient heterogeneous programming framework for managed languages
Oneapi Samples
⭐
758
Samples for Intel® oneAPI Toolkits
E203_hbirdv2
⭐
741
The Ultra-Low Power RISC-V Core
Riscv_vhdl
⭐
552
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
Kianriscv
⭐
396
KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .
Riscv
⭐
364
RISC-V CPU Core (RV32IM)
Nontrivial Mips
⭐
362
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
Biriscv
⭐
300
32-bit Superscalar RISC-V CPU
Forth Cpu
⭐
276
A Forth CPU and System on a Chip, based on the J1, written in VHDL
Ustc Rvsoc
⭐
261
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC,包含一个简单且可扩展的外设总线。
Swapforth
⭐
260
Swapforth is a cross-platform ANS Forth
Riscboy
⭐
204
Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink
Litex Buildenv
⭐
191
An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!
Fpga Chip8
⭐
167
CHIP-8 console on FPGA
Wasmachine
⭐
161
Put WebAssembly in your washing machine
Tekno Kizil
⭐
129
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
Benchmarks
⭐
115
Benchmarking suite to evaluate 🤖 robotics computing performance. Vendor-neutral. ⚪Grey-box and ⚫Black-box approaches.
W11
⭐
109
PDP-11/70 CPU core and SoC
Experiments
⭐
107
Small experiments with attached code
Icestation 32
⭐
107
Compact FPGA game console
Valentyusb
⭐
105
FPGA USB stack written in LiteX
Robotic_processing_unit
⭐
95
A robot-specific processing unit. Contains CPUs, FPGAs and GPUs and maps ROS efficiently to them for best performance.
Oldland Cpu
⭐
89
Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
Lispmicrocontroller
⭐
85
A microcontroller that natively executes a simple LISP dialect
J1sc
⭐
72
A reimplementation of a tiny stack CPU
Shuhai
⭐
71
Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA
Rpu
⭐
70
Basic RISC-V CPU implementation in VHDL.
Elasticsketchcode
⭐
69
Superscalar Riscv Cpu
⭐
69
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
Bit Serial
⭐
65
A bit-serial CPU written in VHDL, with a simulator written in C.
Pasc
⭐
62
Parallel Array of Simple Cores. Multicore processor.
Risc V Fpga
⭐
58
RISC-V CPU for OpenFPGAs, in Icestudio
Nucleusrv
⭐
56
NucleusRV - A 32-bit 5 staged pipelined risc-v core.
Reindeer
⭐
56
PulseRain Reindeer - RISCV RV32I[M] Soft CPU
Riscy Soc
⭐
54
Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
Community
⭐
51
ROS 2 Hardware Acceleration Working Group community governance model & list of projects
Mc1
⭐
49
A computer (FPGA SoC) based on the MRISC32-A1 CPU
Spu32
⭐
48
Small Processing Unit 32: A compact RV32I CPU written in Verilog
Qnice Fpga
⭐
46
QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.
Clash Spaceinvaders
⭐
45
Intel 8080-based Space Invaders arcade machine implemented on an FPGA, written in CLaSH
Opc
⭐
45
One Page CPU Project - CPU, Assembler & Emulator each in a single page of code
Subleq
⭐
43
16-bit SUBLEQ CPU running eForth - just for fun
Hrm Cpu
⭐
43
Human Resource Machine - CPU Design #HRM
Rj32
⭐
42
A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.
Lxp32 Cpu
⭐
42
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
Fuxi
⭐
40
Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
Quafu
⭐
35
A small SoC with a pipeline 32-bit RISC-V CPU.
Risc V Cpu
⭐
34
RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
Phoenix
⭐
34
phoeniX RISC-V Processor
Loongsoncsprj2017
⭐
34
Computer System Project for Loongson FPGA Board in 2017
Managed_ml_systems_and_iot
⭐
32
Managed Machine Learning Systems and Internet of Things Live Lesson
Riscv_cpu
⭐
30
A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
Observer
⭐
28
Proteus
⭐
27
The SpinalHDL design of the Proteus core, an extensible RISC-V core.
Tenyr
⭐
26
Simple, orthogonal 32-bit computer architecture and environment
Fpgacosmacelf
⭐
26
This re-creation of a cosmic ELF computer, Coded in SpinalHDL
Tinymips
⭐
25
The Project TinyMIPS is dedicated to enabling undergraduates to build a complete computer system from scratch.
Smartminerpro
⭐
24
SmartMiner.PRO (SMP) - GUI Multi crypto mining panel for GPU/CPU/ASIC/FPGA
S6soc
⭐
24
CMod-S6 SoC
Fpga_threelevelstorage
⭐
23
【原创,已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计,FPGA三级存储子系统。
Arm9 Compatible Soft Cpu Core
⭐
23
This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
N.i.g.e. Machine
⭐
22
A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is currently hosted on the Digilent Nexys 4 and Nexys 4 DDR
Paas_v1.0
⭐
20
PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
Mark_ii
⭐
20
Simple SoC in VHDL with full toolchain and custom board.
Astrobwt
⭐
20
ASIC/FPGA/GPU resistant CPU mining algorithm.
Ep994a
⭐
18
My TI-99/4A clone, two versions: FPGA+TMS99105 CPU and FPGA with my CPU core
Chad
⭐
18
A self-hosting Forth for J1-style CPUs
Clash Compucolor2
⭐
18
Clash implementation of the Compucolor II home computer
Z80 Fpga
⭐
17
Z80 CPU for OpenFPGAs, with Icestudio
Ti 99_4a_mister
⭐
17
Texas Instrument 99/4A Home Computer
65c02
⭐
15
Implementation of the 65C02 CPU suitable for FPGA.
9444
⭐
15
9444 RISC-V 64IMA CPU and related tools and peripherals.
Gameduino
⭐
14
My own version of the @JamesBowman's Gameduino file repository
Lse Pc
⭐
14
IBM-PC clone based on an Intel 80386SX processor and an Altera Cyclone IV
Icozip
⭐
14
A ZipCPU demonstration port for the icoboard
Riscv Atom
⭐
14
An open-source 32-bit RISC-V soft-core processor for FPGAs.
Digital Resources
⭐
14
Simple Riscv
⭐
13
A simple three-stage RISC-V CPU
Risc8
⭐
13
Mostly AVR compatible FPGA soft-core
Kcores License
⭐
13
KCORES 开源硬件许可证, KCORES 开源硬件协议.
Daphne Benchmark
⭐
12
The Darmstadt Automotive Parallel HeterogeNEous (DAPHNE) Benchmark-Suite
Veriscala
⭐
12
Spinaldev
⭐
12
Docker Development Environment for SpinalHDL
Rv16poc
⭐
12
16 bit RISC-V proof of concept
Ada Picorv32 Example
⭐
12
Example of Ada code running on the PicoRV32 RISC-V CPU for FPGA
Nanofox
⭐
11
A small RISC-V core (SystemVerilog)
Fpganes_release
⭐
11
Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog
Clash Tinybasic
⭐
11
Graphact
⭐
10
[FPGA 2020] Open sourced implementation for the ACM/SIGDA FPGA '20 paper titled "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platforms"
Lionasm
⭐
10
Assembler for Lion CPU
Mera400f
⭐
10
MERA-400 in an FPGA
Nano Cpu32k
⭐
10
Superscalar out-of-order RISC core (with Cache& MMU) and SoC, supporting GNU toolchain & Linux 4.20 kernel, having been verified on Xilinx Kintex-7 FPGA.
Brainf__k_cpu
⭐
10
A CPU that executes brainf**k language. Can be synthesized on FPGA
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