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Search results for risc v systemverilog
risc-v
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systemverilog
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23 search results found
Ibex
⭐
1,169
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Scr1
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688
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Core V Verif
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359
Functional verification project for the CORE-V family of RISC-V cores.
Verigpu
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323
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
Ustc Rvsoc
⭐
261
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC,包含一个简单且可扩展的外设总线。
Core V Mcu
⭐
153
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
Riscv Dbg
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153
RISC-V Debug Support for our PULP RISC-V Cores
Soomrv
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82
A simple superscalar out of order RISC-V (micro)processor
Cheshire
⭐
80
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
Hero
⭐
77
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
Superscalar Riscv Cpu
⭐
69
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
Vicuna
⭐
60
RISC-V Zve32x Vector Coprocessor
Riscv Simple Sv
⭐
56
A simple RISC V core for teaching
Parallella Riscv
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55
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
Aps Reborn
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45
Методические материалы по разработке процессора архитектуры RISC-V
Kronos
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39
Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
Axi Crossbar
⭐
38
An AXI4 crossbar implementation in SystemVerilog
Fpu
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37
IEEE 754 floating point library in system-verilog and vhdl
Cva6 Softcore Contest
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31
National RISC-V student contest CV32A6
Riscv Vip
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29
For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
Gpcore
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28
This is the base repo for our graduation project in AlexU 21
Fpu Sp
⭐
19
IEEE 754 floating point library in system-verilog and vhdl
Mill
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17
RV32I by cats
Drim S
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16
DUTH RISC-V Superscalar Microprocessor
Azadi Soc
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16
Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
Clic
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13
RISC-V fast interrupt controller
Projeto_ih_risc V
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13
Arquivos base para o projeto da disciplina Infraestrutura de Hardware (IF674) no CIn-UFPE.
Awesome Fpga List
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12
A collection of some awesome public FPGA projects.
Friscv
⭐
12
RISCV CPU implementation in SystemVerilog
Nanofox
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11
A small RISC-V core (SystemVerilog)
Ahb3lite_timer
⭐
10
RISC-V compliant Timer IP
Croyde Riscv
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10
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
Rvc_asap
⭐
8
riscv-core-as-simple-as-passible
Fpga_mafia
⭐
8
Designing a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.
Pequeno_riscv
⭐
8
Pequeno aka pqr5 is a pipelined in-order RISC-V CPU Core compliant with RV32I
Pito_riscv
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8
A Barrel design of RV32I
Rp32
⭐
6
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
Procyon
⭐
5
Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.
Armleocpu
⭐
5
Multicore RISC-V CPU RV64GC w/ MMU, Cache. Capable of booting Linux. Work in progress to execute first instruction
Nf5
⭐
5
A simple 5-stage Pipeline RISC-V core
Risc V Core
⭐
5
A repository consisting of all the project files and codes for RISC-V Processor design using Transaction Level Verilog.
Wolv Z0
⭐
5
Wolv Z0 is a RISC-V CPU core
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1-23 of 23 search results
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