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Search results for cpu risc v

53 search results found

Unicorn ⭐ 6,921

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

Vexriscv ⭐ 2,135

A FPGA friendly 32 bit RISC-V CPU implementation

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Darkriscv ⭐ 1,795

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Awesome Cpus ⭐ 1,735

All CPU and MCU documentation in one place

E200_opensource ⭐ 1,688

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Neorv32 ⭐ 1,337

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

E203_hbirdv2 ⭐ 741

The Ultra-Low Power RISC-V Core

Riscv_vhdl ⭐ 552

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Riscv Rust ⭐ 444

RISC-V processor emulator written in Rust+WASM

Kianriscv ⭐ 396

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .

Risc V Single Cycle Cpu ⭐ 380

A RISC-V 32bit single-cycle CPU written in Logisim

RISC-V CPU Core (RV32IM)

Biriscv ⭐ 300

32-bit Superscalar RISC-V CPU

Mipt Mips ⭐ 291

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

RISC-V CPU Core

Riscv Fs ⭐ 268

F# RISC-V Instruction Set formal specification

Ustc Rvsoc ⭐ 261

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Riscboy ⭐ 204

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

Tekno Kizil ⭐ 129

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

Icestation 32 ⭐ 107

Compact FPGA game console

Supervisor Rv ⭐ 96

计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位

XCrypto: a cryptographic ISE for RISC-V

Basic RISC-V CPU implementation in VHDL.

Superscalar Riscv Cpu ⭐ 69

SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.

Schoolriscv ⭐ 67

CPU microarchitecture, step by step

Risc V Computer 2.0 ⭐ 64

An educational RISC-V based computer build with Logisim

Yet another toy CPU.

Nucleusrv ⭐ 56

NucleusRV - A 32-bit 5 staged pipelined risc-v core.

Riscy Soc ⭐ 54

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Rudi Rv32i ⭐ 41

A rudimental RISCV CPU supporting RV32I instructions, in VHDL

Riscv Simulator ⭐ 41

💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

A wrapper for the SPEC CPU2006 benchmark suite.

Cpu Assembly Examples ⭐ 37

CPU assembly examples

A small SoC with a pipeline 32-bit RISC-V CPU.

phoeniX RISC-V Processor

Riscv_cpu ⭐ 30

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

Exactstep ⭐ 29

Instruction set simulator for RISC-V, MIPS and ARM-v6m

Tree Core Cpu ⭐ 29

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

Computer Architecture Task 2 ⭐ 25

Riscv32 CPU Project

Superscalar RISC-V processor written in Clash.

Awesomerisc Vresources ⭐ 22

It contains a curated list of awesome RISC-V Resources.

KISCV, a KISS principle riscv32i CPU

Rift2core ⭐ 21

Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.

Risc 666 ⭐ 20

RISC-V user-mode emulator that runs DooM

RISC-V CPU implementation in Amaranth HDL (aka nMigen)

A RISC-V CPU (Outdated: using priviledge v1.7)

Scarv Cpu ⭐ 18

SCARV: a side-channel hardened RISC-V platform

9444 RISC-V 64IMA CPU and related tools and peripherals.

Riscv Atom ⭐ 14

An open-source 32-bit RISC-V soft-core processor for FPGAs.

Kendryte K210 BSP for RT-Thread

Simple Riscv ⭐ 13

A simple three-stage RISC-V CPU

Riscv32 Cpu Chisel ⭐ 12

Learning how to make RISC-V 32bit CPU with Chisel

16 bit RISC-V proof of concept

Riscv Cpu ⭐ 11

SJTU Computer Architecture(1) Hw

A small RISC-V core (SystemVerilog)

in-line FPGA-CPU协同分组处理

Croyde Riscv ⭐ 10

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

Toy RISC-V emulator

Little Cpu ⭐ 8

Little cpu in verilog.

Computer Architecture ⭐ 8

Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003 , Introduction to Computer Organisation in IIT Madras.

Pequeno_riscv ⭐ 8

Pequeno aka pqr5 is a pipelined in-order RISC-V CPU Core compliant with RV32I

Cpu Judge ⭐ 7

RISC-V SingleCycle/Pipeline CPU (lab of ZJU Computer System Series)

Fpga_riscv_cpu ⭐ 6

fpga verilog risc-v rv32i cpu

Simple Qemu ⭐ 6

Emulating other CPU architectures in Docker made easy

RISC-V CPU plugin for Hopper Disassembler

Risc V Cpu ⭐ 6

A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

Cpu Riscv ⭐ 6

ACM Class 2017 Computer Architecture

Multi-core RISC-V application processor

Fpga_test_soc ⭐ 5

A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)

Armleocpu ⭐ 5

Multicore RISC-V CPU RV64GC w/ MMU, Cache. Capable of booting Linux. Work in progress to execute first instruction

Wolv Z0 is a RISC-V CPU core

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