Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Unicorn | 6,921 | 4 | 3 months ago | 8 | November 01, 2022 | 87 | gpl-2.0 | C | ||
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86) | ||||||||||
Vexriscv | 2,135 | 4 months ago | 100 | mit | Assembly | |||||
A FPGA friendly 32 bit RISC-V CPU implementation | ||||||||||
Cva6 | 2,042 | a month ago | 157 | other | Assembly | |||||
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux | ||||||||||
Darkriscv | 1,795 | 5 months ago | 9 | bsd-3-clause | Verilog | |||||
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! | ||||||||||
Awesome Cpus | 1,735 | a year ago | 1 | cc0-1.0 | HTML | |||||
All CPU and MCU documentation in one place | ||||||||||
E200_opensource | 1,688 | 3 years ago | 33 | apache-2.0 | Verilog | |||||
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2 | ||||||||||
Neorv32 | 1,337 | 3 months ago | 15 | bsd-3-clause | VHDL | |||||
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. | ||||||||||
E203_hbirdv2 | 741 | a year ago | 10 | apache-2.0 | Verilog | |||||
The Ultra-Low Power RISC-V Core | ||||||||||
Riscv_vhdl | 552 | 4 months ago | 2 | apache-2.0 | Verilog | |||||
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators | ||||||||||
Riscv Rust | 444 | 1 | a year ago | 6 | July 02, 2020 | 41 | mit | Rust | ||
RISC-V processor emulator written in Rust+WASM |