Tree Core Cpu
A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Darkriscv | 1,795 | 5 months ago | 9 | bsd-3-clause | Verilog | |||||
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! | ||||||||||
| Riscv_vhdl | 552 | 4 months ago | 2 | apache-2.0 | Verilog | |||||
| Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators | ||||||||||
| Concurrency | 537 | 2 years ago | 2 | Java | ||||||
| Java 并发编程知识梳理以及常见处理模式 features and patterns | ||||||||||
| Nontrivial Mips | 362 | 4 years ago | other | SystemVerilog | ||||||
| NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux. | ||||||||||
| Ustc Rvsoc | 261 | 7 months ago | 4 | gpl-3.0 | SystemVerilog | |||||
| An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。 | ||||||||||
| Tekno Kizil | 129 | 9 months ago | 3 | gpl-3.0 | Verilog | |||||
| KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi | ||||||||||
| Toooba | 126 | 9 months ago | 3 | other | Verilog | |||||
| RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT | ||||||||||
| Oldland Cpu | 89 | 8 years ago | 1 | Verilog | ||||||
| Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools | ||||||||||
| Realtek Mips Sdks | 50 | a year ago | C | |||||||
| Realtek Network SoC/CPU toolchains (including support for Lexra based chips) | ||||||||||
| Simplecpu | 30 | 4 years ago | 5 | bsd-3-clause | C | |||||
| An open source CPU design and verification platform for academia | ||||||||||
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