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Search results for rtl risc v

16 search results found

Rocket Chip ⭐ 2,988

Rocket Chip Generator

Darkriscv ⭐ 1,795

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Riscv Boom ⭐ 1,524

SonicBOOM: The Berkeley Out-of-Order Machine

Chipyard ⭐ 1,393

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Firesim ⭐ 778

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

Cores Veer Eh1 ⭐ 770

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Riscv_vhdl ⭐ 552

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Riscv Mini ⭐ 427

Simple RISC-V 3-stage Pipeline in Chisel

Core V Verif ⭐ 359

Functional verification project for the CORE-V family of RISC-V cores.

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

Ustc Rvsoc ⭐ 261

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Cores Veer El2 ⭐ 222

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

Saxonsoc ⭐ 133

SoC based on VexRiscv and ICE40 UP5K

Tekno Kizil ⭐ 129

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

Imperas Riscv Tests ⭐ 123

Simple 3-stage pipeline RISC-V processor

Lm Riscv Dv ⭐ 41

An Open-Source Design and Verification Environment for RISC-V

rfuzz: coverage-directed fuzzing for RTL research platform

Tree Core Cpu ⭐ 29

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

Boom Template ⭐ 23

A template for building new projects/platforms using the BOOM core.

QuSoC demo projects and template

Quasar 2.0: Chisel equivalent of SweRV-EL2

Awesome Fpga List ⭐ 12

A collection of some awesome public FPGA projects.

RISC-V BSV Specification

Rocket Chip Rocc ⭐ 8

This repo contains source files and code for a synthesizable RISC-V processor with support for custom instructions in a co-processor.

32-bit soft RISCV processor for FPGA applications

Pequeno_riscv ⭐ 8

Pequeno aka pqr5 is a pipelined in-order RISC-V CPU Core compliant with RV32I

BOOM's Simulation Accelerator.

Pint_iverilog ⭐ 5

Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.

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