Chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Chipyard | 1,393 | a month ago | 170 | bsd-3-clause | C | |||||
| An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more | ||||||||||
| Hw | 1,254 | 2 years ago | 193 | other | Verilog | |||||
| RTL, Cmodel, and testbench for NVDLA | ||||||||||
| Esp | 267 | 4 months ago | 34 | other | C | |||||
| Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy | ||||||||||
| Bigpulp | 48 | 2 years ago | 8 | other | SystemVerilog | |||||
| ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform | ||||||||||
| Awslabs | 23 | 5 years ago | TeX | |||||||
| Hls Cnn | 19 | 4 months ago | mit | C | ||||||
| High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition. | ||||||||||
| Pymtl Tut Hls | 8 | 8 years ago | C++ | |||||||
| Tutorial for integrating PyMTL and Vivado HLS | ||||||||||
| Bossa | 6 | 2 years ago | other | Scala | ||||||
| BOOM's Simulation Accelerator. | ||||||||||
| Melodica | 5 | 3 years ago | 5 | apache-2.0 | Bluespec | |||||
| A posit arithmetic unit which implements Quire. Designed to be used both as a functional unit or as a tightly coupled accelerator. | ||||||||||
Alternatives To ChipyardSelect To Compare
Alternative Project Comparisons
Popular Accelerator Projects
Popular Rtl Projects
Popular Software Performance Categories
Get A Weekly Email With Trending Projects For These Categories
No Spam. Unsubscribe easily at any time.
Rtl
Risc V
Accelerator