Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Rocket Chip | 2,988 | a month ago | 9 | May 14, 2020 | 269 | other | Scala | |||
Rocket Chip Generator | ||||||||||
Darkriscv | 1,795 | 5 months ago | 9 | bsd-3-clause | Verilog | |||||
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! | ||||||||||
Riscv Boom | 1,524 | 3 months ago | 98 | bsd-3-clause | Scala | |||||
SonicBOOM: The Berkeley Out-of-Order Machine | ||||||||||
Chipyard | 1,393 | a month ago | 170 | bsd-3-clause | C | |||||
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more | ||||||||||
Firesim | 778 | 3 months ago | 218 | other | Scala | |||||
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility | ||||||||||
Cores Veer Eh1 | 770 | a year ago | 14 | apache-2.0 | SystemVerilog | |||||
VeeR EH1 core | ||||||||||
Scr1 | 688 | 7 months ago | 3 | other | SystemVerilog | |||||
SCR1 is a high-quality open-source RISC-V MCU core in Verilog | ||||||||||
Riscv_vhdl | 552 | 4 months ago | 2 | apache-2.0 | Verilog | |||||
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators | ||||||||||
Riscv Mini | 427 | 7 months ago | 3 | other | Scala | |||||
Simple RISC-V 3-stage Pipeline in Chisel | ||||||||||
Core V Verif | 359 | 3 months ago | 116 | other | Assembly | |||||
Functional verification project for the CORE-V family of RISC-V cores. |