Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Ibex | 1,169 | 3 months ago | 185 | apache-2.0 | SystemVerilog | |||||
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. | ||||||||||
Freezing Spice | 88 | 5 years ago | 2 | bsd-3-clause | VHDL | |||||
A pipelined RISCV implementation in VHDL | ||||||||||
Riscv Simple Sv | 56 | 2 years ago | bsd-3-clause | SystemVerilog | ||||||
A simple RISC V core for teaching | ||||||||||
Riscv Asic | 8 | 6 years ago | ||||||||
RISC-V ASIC design reference | ||||||||||
Ncore | 6 | 4 years ago | other | C++ | ||||||
A RISCV processor in system verilog |