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46 search results found

Verilator ⭐ 1,934

Verilator open-source SystemVerilog simulator and lint system

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Nontrivial Mips ⭐ 362

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

Core V Verif ⭐ 359

Functional verification project for the CORE-V family of RISC-V cores.

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

Deepfloat ⭐ 333

An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.

Code generation tool for configuration and status registers

Ustc Rvsoc ⭐ 261

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Sv Tests ⭐ 257

Test suite designed to check compliance with the SystemVerilog standard.

Veryl: A Modern Hardware Description Language

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Fpga Ftdi245fifo ⭐ 178

FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

Open Register Design Tool ⭐ 169

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Fpga Sdcard Reader ⭐ 142

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

Fpga Jpeg Ls Encoder ⭐ 141

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Fpga Can ⭐ 121

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

Verilog Fixedpoint ⭐ 75

A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

Fpga Sdfake ⭐ 69

Imitate SDcard using FPGAs. 使用FPGA模拟(伪装) SD卡。

Fpga Png Decoder ⭐ 57

An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图象解码器，可以从PNG文件中解码出原始像素。

Fpga Sdcard Reader Spi ⭐ 52

An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线)，可以从FAT16或FAT32格式的SD卡中读取文件。

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform

Verilog Sha Family ⭐ 43

Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。

Crash_course_for_new_members ⭐ 26

Deep Learning & VLSI Crash Course for New Members

Basic Common Modules

Hdlconvertorast ⭐ 25

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

Deepfreeze ⭐ 21

Intel Training Modules ⭐ 20

Riscv Multi Core Lotr ⭐ 19

RISCV core RV32I/E.4 threads in a ring architecture

Virtio implementation in SystemVerilog

This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).

SystemVerilog FSM generator

Awesome Fpga List ⭐ 12

A collection of some awesome public FPGA projects.

Uvm_tb_cross_bar ⭐ 11

SystemVerilog UVM testbench example

Digital Hardware Modelling ⭐ 11

Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

Fpga_snark_prover ⭐ 9

An acceleration engine for proving SNARKS over the bn128 curve, targeted for AWS FPGAs

Rggen Systemverilog ⭐ 9

SystemVerilog RTL and UVM RAL model generators for RgGen

Open source RTL simulation acceleration on commodity hardware

Blockwork ⭐ 9

An opinionated build environment for EDA projects

Peakrdl Verilog ⭐ 8

Generate verilog register file from systemRDL description

Tinylabs Cores ⭐ 8

Fusesoc compatible rtl cores

Pequeno_riscv ⭐ 8

Pequeno aka pqr5 is a pipelined in-order RISC-V CPU Core compliant with RV32I

Tia Infrastructure ⭐ 6

RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.

Sphinx Verilog Domain ⭐ 5

Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.

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