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Search results for vhdl rtl

29 search results found

Spinalhdl ⭐ 1,451

Scala based HDL

Openwifi Hw ⭐ 560

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Riscv_vhdl ⭐ 552

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Code generation tool for configuration and status registers

A huge VHDL library for FPGA development

Bladerf Wiphy ⭐ 255

bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Spinalcrypto ⭐ 36

SpinalHDL - Cryptography libraries

hardware library for hwt (= ipcore repo)

Fpga_examples ⭐ 29

Example code in vhdl to help starting new projects using FPGA devices.

Hdlconvertorast ⭐ 25

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

Design And Asic Implementation Of 32 Point Fft Processor ⭐ 20

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of a

Ctu Can Fd ⭐ 15

This is a mirror repository for official CTU CAN FD repository:

Spinaldev ⭐ 12

Docker Development Environment for SpinalHDL

Rggen Vhdl ⭐ 12

VHDL plugin for RgGen

Zynq Pynq Z2 Gobang ⭐ 11

参加2018第二届全国大学生FPGA创新设计邀请赛的作品

Digital Hardware Modelling ⭐ 11

Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

Hdl Modules ⭐ 10

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Custom 64-bit pipelined RISC processor

Multi-function, universal, fixed-point CORDIC

Rtl Coding ⭐ 6

"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"

Systolicarray ⭐ 6

A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.

Sha 256 Hdl ⭐ 6

An implementation of original SHA-256 hash function in (RTL) VHDL

Nexys4ddr Arm M3 Plate Recognition ⭐ 5

车牌识别,FPGA,2019全国大学生集成电路创新创业大赛

Describing RTL circuit in Ruby

Meowrouter Top ⭐ 5

Top for MeowRouter

Lzw_verilog ⭐ 5

LZW Compressoion algorithm in verilog

Bonfire_legacy ⭐ 5

A Fault Tolerant NoC Architecture

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1-29 of 29 search results

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