Verilog Fixedpoint
A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Darkriscv | 1,795 | 5 months ago | 9 | bsd-3-clause | Verilog | |||||
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! | ||||||||||
| Xls | 1,087 | 3 months ago | 607 | apache-2.0 | C++ | |||||
| XLS: Accelerated HW Synthesis | ||||||||||
| Verilog Fixedpoint | 75 | 8 months ago | gpl-3.0 | Verilog | ||||||
| A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。 | ||||||||||
| Bch_verilog | 57 | 2 years ago | 4 | other | Verilog | |||||
| Verilog based BCH encoder/decoder | ||||||||||
| Mips Pipeline Processor | 52 | 5 years ago | 1 | Verilog | ||||||
| A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding | ||||||||||
| Autopiper | 40 | 9 years ago | apache-2.0 | C++ | ||||||
| Risc V Cpu | 34 | 6 years ago | 1 | Verilog | ||||||
| RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL. | ||||||||||
| Computer Architecture Task 2 | 25 | 6 years ago | mit | Verilog | ||||||
| Riscv32 CPU Project | ||||||||||
| Fast | 22 | 7 years ago | apache-2.0 | Verilog | ||||||
| FAST | ||||||||||
| Tinycpu | 21 | 12 years ago | Verilog | |||||||
| Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes. | ||||||||||
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