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Search results for systemverilog asic
asic
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systemverilog
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19 search results found
Clash Compiler
⭐
1,336
Haskell to VHDL/Verilog/SystemVerilog compiler
Axi
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834
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Rggen
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261
Code generation tool for configuration and status registers
Open Register Design Tool
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169
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Logic
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121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Cheshire
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80
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
Corsair
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52
Control and Status Register map generator for HDL projects
Peakrdl
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48
Control and status register code generator toolchain
Axi Crossbar
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38
An AXI4 crossbar implementation in SystemVerilog
Peakrdl Regblock
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36
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Shunt
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29
SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
Deepsocflow
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28
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
My Verilog Examples
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22
A place to keep my synthesizable verilog examples.
Friscv
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12
RISCV CPU implementation in SystemVerilog
Svlogger
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11
SystemVerilog Logger
S Link
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8
An Open Source Link Protocol and Controller
Peakrdl Verilog
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8
Generate verilog register file from systemRDL description
Apogeorv
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6
A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
Libsv
⭐
6
An open source, parameterized SystemVerilog digital hardware IP library
Rp32
⭐
6
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
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1-19 of 19 search results
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