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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Clash Compiler ⭐ 1,336

Haskell to VHDL/Verilog/SystemVerilog compiler

SERV - The SErial RISC-V CPU

Fusesoc ⭐ 1,065

Package manager and build abstraction tool for FPGA/ASIC development

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Riscv Cores List ⭐ 791

RISC-V Cores, SoC platforms and SoCs

VUnit is a unit testing framework for VHDL/SystemVerilog

Embedded Neural Network ⭐ 547

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

RISC-V CPU Core (RV32IM)

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Various HDL (Verilog) IP Cores

Biriscv ⭐ 300

32-bit Superscalar RISC-V CPU

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

Code generation tool for configuration and status registers

A huge VHDL library for FPGA development

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Open source machine learning accelerators

Systemrdl Compiler ⭐ 212

SystemRDL 2.0 language compiler front-end

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Async_fifo ⭐ 173

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Ztachip ⭐ 172

Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.

Mflowgen ⭐ 169

mflowgen -- A Modular ASIC/FPGA Flow Generator

Open Register Design Tool ⭐ 169

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Awesome Fpga ⭐ 150

A collection of resources on FPGA devices and development in general

Usb_cdc ⭐ 131

Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs

Tekno Kizil ⭐ 129

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

My Cheat Sheets ⭐ 121

A place to keep all my cheat sheets for the complete development of ASIC/FPGA hardware or a software app/service.

Neotrng ⭐ 113

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

Awesome Riscv ⭐ 96

😎 A curated list of awesome RISC-V implementations

HW Design: A Functional Approach

Kamikaze ⭐ 88

Light-weight RISC-V RV32IMC microcontroller core.

Cheshire ⭐ 80

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

DFiant: A Dataflow Hardware Descripition Language

Control and Status Register map generator for HDL projects

Control and status register code generator toolchain

Airisc_core_complex ⭐ 48

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals for embedded AI applications and smart sensors.

Siafpgaminer ⭐ 44

VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin

Hdlab Fpga Development Board ⭐ 43

Open source FPGA development platform

Peakrdl Uvm ⭐ 41

Generate UVM register model from compiled SystemRDL input

Awesome Hwd Tools ⭐ 41

A curated list of awesome open source hardware design tools

Peakrdl Html ⭐ 40

Generate address space documentation HTML from compiled SystemRDL input

Axi Crossbar ⭐ 38

An AXI4 crossbar implementation in SystemVerilog

Peakrdl Regblock ⭐ 36

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Neorv32 Verilog ⭐ 35

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

Structural Netlist API (and more) for EDA post synthesis flow development

Vga Clock ⭐ 33

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Peakrdl Ipxact ⭐ 29

Import and export IP-XACT XML register models

Deepsocflow ⭐ 28

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

Open source RISC-V IP core for FPGA/ASIC design

Smartminerpro ⭐ 24

SmartMiner.PRO (SMP) - GUI Multi crypto mining panel for GPU/CPU/ASIC/FPGA

Suqa Core ⭐ 23

Neochips ⭐ 23

Replacement "chips" for NeoGeo systems

My Verilog Examples ⭐ 22

A place to keep my synthesizable verilog examples.

A Heterogeneous Platform Deep Learning Compiler Framework from EdgeCortix

Sm3_core ⭐ 21

Design And Asic Implementation Of 32 Point Fft Processor ⭐ 20

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of a

Eda Scripts ⭐ 20

Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)

Astrobwt ⭐ 20

ASIC/FPGA/GPU resistant CPU mining algorithm.

A self-hosting Forth for J1-style CPUs

Open Cryptonight Asic ⭐ 16

Open source hardware implementation of classic CryptoNight

Gatery, a library for circuit design.

Aes Gcm 128 192 256 Bits ⭐ 14

Configurable AES-GCM IP (128, 192, 256 bits)

A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration

RISCV CPU implementation in SystemVerilog

Fpga_cryptonight_v7 ⭐ 12

FPGA CryptoNight V7 Minner

100daysofrtl ⭐ 12

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

Svlogger ⭐ 11

SystemVerilog Logger

Omnixtendendpoint ⭐ 10

Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.

RISC-V ISA based 32-bit processor written in HLS

Hdl Modules ⭐ 10

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Thdl is a tool for easing the work with hardware description languages.

Spinalhdl Template ⭐ 8

Mill template for beginning your SpinalHDL project

An Open Source Link Protocol and Controller

Awesome Digital Ic ⭐ 8

A collection of great digital IC project/tutorial/website etc..

Peakrdl Verilog ⭐ 8

Generate verilog register file from systemRDL description

Mastering Fpgasic Book ⭐ 8

📖 Mastering FPGASIC Book

Vdf Fpga Round2 Results ⭐ 7

high abstraction synthesis

Bfgminer Ansible ⭐ 7

Deploy ASIC/FPGA/GPU miners with ansible

Regenerate ⭐ 7

Manages registers for ASIC and FPGA designs

An open source, parameterized SystemVerilog digital hardware IP library

RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

Lightweight UART core in VHDL

Gost 28147 89 ⭐ 5

Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher

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