Project Name	Stars	Repos Using This	Packages Using This	Most Recent Commit	Total Releases	Latest Release	Open Issues	License	Language
Fusesoc	1,065	5	5	3 months ago	26	November 17, 2023	119	bsd-2-clause	Python
Package manager and build abstraction tool for FPGA/ASIC development
Vtr Verilog To Routing	925			3 months ago			447	other	C++
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Openfpga	692			3 months ago			103	mit	Verilog
An Open-source FPGA IP Generator
Edalize	573	2	3	3 months ago	24	December 08, 2023	91	bsd-2-clause	Python
An abstraction library for interfacing EDA tools
Rggen	261			3 months ago	62	October 18, 2023	11	mit	Ruby
Code generation tool for configuration and status registers
Systemrdl Compiler	212	3	14	3 months ago	50	November 09, 2023	8	mit	Python
SystemRDL 2.0 language compiler front-end
Open Register Design Tool	169			9 months ago			23	apache-2.0	Verilog
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Kactus2dev	168			3 months ago			17	gpl-2.0	C++
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
Ice Chips Verilog	99			a year ago			4	gpl-3.0	Verilog
IceChips is a library of all common discrete logic devices in Verilog
Yosys F4pga Plugins	81			3 months ago			83	apache-2.0	Verilog
Plugins for Yosys developed as part of the F4PGA project.

Alternatives To Systemrdl Compiler

Select To Compare

Fusesoc ⭐ 1,065

Package manager and build abstraction tool for FPGA/ASIC development

dependent packages 5total releases 26most recent commit 3 months ago

Vtr Verilog To Routing ⭐ 925

Verilog to Routing -- Open Source CAD Flow for FPGA Research

most recent commit 3 months ago

Openfpga ⭐ 692

An Open-source FPGA IP Generator

most recent commit 3 months ago

Edalize ⭐ 573

An abstraction library for interfacing EDA tools

dependent packages 3total releases 24most recent commit 3 months ago

Rggen ⭐ 261

Code generation tool for configuration and status registers

total releases 62most recent commit 3 months ago

Systemrdl Compiler ⭐ 212

SystemRDL 2.0 language compiler front-end

dependent packages 14total releases 50most recent commit 3 months ago

Open Register Design Tool ⭐ 169

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

most recent commit 9 months ago

Kactus2dev ⭐ 168

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

most recent commit 3 months ago

Ice Chips Verilog ⭐ 99

IceChips is a library of all common discrete logic devices in Verilog

most recent commit a year ago

Yosys F4pga Plugins ⭐ 81

Plugins for Yosys developed as part of the F4PGA project.

most recent commit 3 months ago

Suggest An Alternative To systemrdl-compiler

Alternative Project Comparisons

Systemrdl Compiler vs Fusesoc

Systemrdl Compiler vs Vtr Verilog To Routing

Systemrdl Compiler vs Openfpga

Systemrdl Compiler vs Edalize

Systemrdl Compiler vs Rggen

Systemrdl Compiler vs Open Register Design Tool

Systemrdl Compiler vs Kactus2dev

Systemrdl Compiler vs Ice Chips Verilog

Systemrdl Compiler vs Yosys F4pga Plugins

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