Aes
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Aes | 238 | a year ago | 1 | bsd-2-clause | Verilog | |||||
| Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys. | ||||||||||
| Aes | 20 | 2 years ago | 1 | mit | Verilog | |||||
| Advanced encryption standard implementation in verilog. | ||||||||||
| Oram | 12 | 7 years ago | 3 | Verilog | ||||||
| Hardware implementation of ORAM | ||||||||||
| Aes_chisel | 10 | 2 years ago | 2 | April 04, 2019 | apache-2.0 | Scala | ||||
| Implementation of the Advanced Encryption Standard in Chisel | ||||||||||
| Oram | 9 | 9 years ago | 1 | Verilog | ||||||
| Recursive unified ORAM | ||||||||||
| Rc4 Prbs | 7 | 11 years ago | lgpl-3.0 | Verilog | ||||||
| A Verilog open-source implementation of a RC4 encryption algorigthm using a pseudorandom binary sequence (PRBS) for FPGA synthesis. | ||||||||||
| Fpga_sm4 | 6 | 6 years ago | gpl-3.0 | Verilog | ||||||
| FPGA implementation of Chinese SM4 encryption algorithm. | ||||||||||
| Sm4 Verilog | 5 | 5 years ago | gpl-3.0 | Verilog | ||||||
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Aes
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