Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Cva6 | 2,042 | 21 days ago | 157 | other | Assembly | |||||
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux | ||||||||||
Clash Compiler | 1,336 | 44 | 3 months ago | 87 | November 11, 2023 | 280 | other | Haskell | ||
Haskell to VHDL/Verilog/SystemVerilog compiler | ||||||||||
Serv | 1,158 | 4 months ago | 17 | isc | Verilog | |||||
SERV - The SErial RISC-V CPU | ||||||||||
Fusesoc | 1,065 | 5 | 5 | 3 months ago | 26 | November 17, 2023 | 119 | bsd-2-clause | Python | |
Package manager and build abstraction tool for FPGA/ASIC development | ||||||||||
Axi | 834 | 4 months ago | 49 | other | SystemVerilog | |||||
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication | ||||||||||
Riscv Cores List | 778 | 3 years ago | n,ull | |||||||
RISC-V Cores, SoC platforms and SoCs | ||||||||||
Vunit | 678 | 1 | 5 | 17 days ago | 87 | April 23, 2023 | 216 | other | VHDL | |
VUnit is a unit testing framework for VHDL/SystemVerilog | ||||||||||
Embedded Neural Network | 547 | 3 months ago | n,ull | |||||||
collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning | ||||||||||
Riscv | 364 | 3 years ago | 4 | bsd-3-clause | Verilog | |||||
RISC-V CPU Core (RV32IM) | ||||||||||
Poc | 324 | 4 years ago | 31 | other | VHDL | |||||
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany |