Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Learn Fpga | 2,225 | 3 months ago | 36 | bsd-3-clause | C++ | |||||
Learning FPGA, yosys, nextpnr, and RISC-V | ||||||||||
Vitis Tutorials | 972 | 3 months ago | 58 | mit | C | |||||
Vitis In-Depth Tutorials | ||||||||||
Dsp Theory | 792 | a year ago | 1 | gpl-3.0 | Jupyter Notebook | |||||
Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc. | ||||||||||
Oneapi Samples | 758 | 3 months ago | 61 | mit | C++ | |||||
Samples for Intel® oneAPI Toolkits | ||||||||||
Openfpga | 692 | 3 months ago | 103 | mit | Verilog | |||||
An Open-source FPGA IP Generator | ||||||||||
Hls4ml Tutorial | 245 | 24 days ago | 18 | Jupyter Notebook | ||||||
Tutorial notebooks for hls4ml | ||||||||||
Awesome Fpga | 150 | 7 years ago | gpl-3.0 | |||||||
A collection of resources on FPGA devices and development in general | ||||||||||
Fpga Partial Reconfig | 84 | 3 months ago | 1 | mit | SystemVerilog | |||||
Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow | ||||||||||
Sdaccel Tutorials | 75 | 4 years ago | 7 | C++ | ||||||
SDAccel Development Environment Tutorials | ||||||||||
Qnice Fpga | 46 | 3 years ago | 76 | other | Assembly | |||||
QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL. |