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Search results for verilog asic

60 search results found

Clash Compiler ⭐ 1,336

Haskell to VHDL/Verilog/SystemVerilog compiler

SERV - The SErial RISC-V CPU

Openlane ⭐ 1,148

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Fusesoc ⭐ 1,065

Package manager and build abstraction tool for FPGA/ASIC development

RISC-V CPU Core (RV32IM)

Various HDL (Verilog) IP Cores

Biriscv ⭐ 300

32-bit Superscalar RISC-V CPU

Code generation tool for configuration and status registers

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Async_fifo ⭐ 173

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Open Register Design Tool ⭐ 169

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Qflow full end-to-end digital synthesis flow for ASIC designs

Awesome Fpga ⭐ 150

A collection of resources on FPGA devices and development in general

Usb_cdc ⭐ 131

Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs

Tekno Kizil ⭐ 129

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Openlane2 ⭐ 99

The next generation of OpenLane, rewritten from scratch with a modular architecture

Kamikaze ⭐ 88

Light-weight RISC-V RV32IMC microcontroller core.

Awesome Dv ⭐ 76

Awesome ASIC design verification

Verilog Parser ⭐ 68

A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

Control and Status Register map generator for HDL projects

Airisc_core_complex ⭐ 48

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals for embedded AI applications and smart sensors.

Control and status register code generator toolchain

Tt05 Psg Sn76489 ⭐ 42

TinyTapeout submission with the SN76489 Digital Complex Sound Generator (DCSG) programmable sound generator (PSG) chip from Texas Instruments.

Axi Crossbar ⭐ 38

An AXI4 crossbar implementation in SystemVerilog

Neorv32 Verilog ⭐ 35

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

Structural Netlist API (and more) for EDA post synthesis flow development

Vga Clock ⭐ 33

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)

Deepsocflow ⭐ 28

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

Neochips ⭐ 23

Replacement "chips" for NeoGeo systems

My Verilog Examples ⭐ 22

A place to keep my synthesizable verilog examples.

Sm3_core ⭐ 21

Design And Asic Implementation Of 32 Point Fft Processor ⭐ 20

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of a

A self-hosting Forth for J1-style CPUs

Open Cryptonight Asic ⭐ 16

Open source hardware implementation of classic CryptoNight

Globalfoundries Pdk Libs Gf180mcu_fd_sc_mcu7t5v0 ⭐ 16

7 track standard cells for GF180MCU provided by GlobalFoundries.

Globalfoundries Pdk Libs Gf180mcu_fd_sc_mcu9t5v0 ⭐ 14

9 track standard cells for GF180MCU provided by GlobalFoundries.

Fpga_cryptonight_v7 ⭐ 12

FPGA CryptoNight V7 Minner

Moneroasic ⭐ 12

Cryptonight Monero Verilog code for ASIC

RISCV CPU implementation in SystemVerilog

Globalfoundries Pdk Ip Gf180mcu_fd_ip_sram ⭐ 12

SRAM macros created for the GF180MCU provided by GlobalFoundries.

100daysofrtl ⭐ 12

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

Svlogger ⭐ 11

SystemVerilog Logger

Globalfoundries Pdk Libs Gf180mcu_fd_io ⭐ 11

IO and periphery cells for the GF180MCU provided by GlobalFoundries.

Arm Cortex-M0 based Customizable SoC for IoT Applications

Vsdstdcelldesign ⭐ 9

This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.

An Open Source Link Protocol and Controller

Mastering Fpgasic Book ⭐ 8

📖 Mastering FPGASIC Book

Christmastreecontroller ⭐ 8

Christmas tree controller (ASIC)

Peakrdl Verilog ⭐ 8

Generate verilog register file from systemRDL description

The SAP-1 in Verilog, and now as an ASIC!

Wrapped_rgb_mixer ⭐ 7

Demo project for the Zero to ASIC Course.

Frequency_counter ⭐ 6

Project 2.2 Frequency counter

Instrumented_adder ⭐ 6

Instrumenting adders to measure speed

An open source, parameterized SystemVerilog digital hardware IP library

Alogic is a Medium Level Synthesis language for digital logic that compiles swiftly into standard Verilog-2005 for implementation in ASIC or FPGA.

Gost 28147 89 ⭐ 5

Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher

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