Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Clash Compiler | 1,336 | 44 | 3 months ago | 87 | November 11, 2023 | 280 | other | Haskell | ||
Haskell to VHDL/Verilog/SystemVerilog compiler | ||||||||||
Serv | 1,158 | 4 months ago | 17 | isc | Verilog | |||||
SERV - The SErial RISC-V CPU | ||||||||||
Openlane | 1,148 | a month ago | 138 | apache-2.0 | Python | |||||
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization. | ||||||||||
Fusesoc | 1,065 | 5 | 5 | 3 months ago | 26 | November 17, 2023 | 119 | bsd-2-clause | Python | |
Package manager and build abstraction tool for FPGA/ASIC development | ||||||||||
Riscv | 364 | 3 years ago | 4 | bsd-3-clause | Verilog | |||||
RISC-V CPU Core (RV32IM) | ||||||||||
Cores | 302 | 3 years ago | 3 | Verilog | ||||||
Various HDL (Verilog) IP Cores | ||||||||||
Biriscv | 300 | 3 years ago | 8 | apache-2.0 | Verilog | |||||
32-bit Superscalar RISC-V CPU | ||||||||||
Rggen | 261 | 3 months ago | 62 | October 18, 2023 | 11 | mit | Ruby | |||
Code generation tool for configuration and status registers | ||||||||||
Aes | 238 | a year ago | 1 | bsd-2-clause | Verilog | |||||
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys. | ||||||||||
Async_fifo | 173 | a year ago | other | Verilog | ||||||
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog |