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Vexriscv ⭐ 2,135

A FPGA friendly 32 bit RISC-V CPU implementation

Neorv32 ⭐ 1,337

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

E203_hbirdv2 ⭐ 741

The Ultra-Low Power RISC-V Core

Riscv_vhdl ⭐ 552

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Ustc Rvsoc ⭐ 261

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Code generation tool for configuration and status registers

Caravel ⭐ 223

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.

Libsystemctlm Soc ⭐ 175

SystemC/TLM-2.0 Co-simulation framework

Iob Soc ⭐ 131

RISC-V System on Chip Template

Milkymist ⭐ 123

SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU

Tang_e203_mini ⭐ 103

LicheeTang 蜂鸟E203 Core

Oldland Cpu ⭐ 89

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

Naivemips Hdl ⭐ 63

Naïve MIPS32 SoC implementation

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

Riscy Soc ⭐ 54

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

Icez0mb1e ⭐ 49

FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC

Ultramips_nscscc ⭐ 47

UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.

Vexriscvsoftcorecontest2018 ⭐ 46

An experimental System-on-Chip with a custom compiler toolchain.

Moxie Cores ⭐ 45

Moxie-compatible core repository

Neorv32 Setups ⭐ 44

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

A port of Linux to the OWON SDS7102 scope

Bit_nscscc_suggestion ⭐ 38

为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助

Axi Crossbar ⭐ 38

An AXI4 crossbar implementation in SystemVerilog

hardware library for hwt (= ipcore repo)

IBM PC Compatible SoC for a commercially available FPGA board

mirror of https://git.elphel.com/Elphel/x393

Notary: A Device for Secure Transaction Approval 📟

Ddk Fpga ⭐ 25

FPGA HDL Sources.

Riscv Soc Cores ⭐ 23

Fpga_ultrasound ⭐ 22

CMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system.

Edabk_brain_soc ⭐ 20

A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated by ChatGPT-4 with advanced optimizations.

Lemoncore ⭐ 20

Simple RISC-V processor for FPGAs 🍋 🤖

Design And Asic Implementation Of 32 Point Fft Processor ⭐ 20

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of a

The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is not related in any way with Minimig - it is a new and independent Amiga OCS implementation.

Picorv32_xilinx ⭐ 19

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

Picoblaze Library ⭐ 18

The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).

This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).

Vsdmixedsignalflow ⭐ 16

This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also discusses the steps to modify the current IP layouts inorder to ensure its acceptance by the EDA tools.

Usb2_dev ⭐ 16

USB 2.0 Device IP Core

Tinyfpga Bx Game Soc ⭐ 16

A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games

Sha256hasher ⭐ 15

SHA-256 IP core for ZedBoard (Zynq SoC)

Posture_recognition_cnn ⭐ 14

To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different responses to all kinds of human's postures. But the process is very difficult as well, because usually it is very slow and power-consuming, and requires a very large memory space. Here we focus on real-time posture recognition, and try to make the machine "know" what posture we make. The posture recognition system is consisted of DE10-Nano SoC FPGA Kit, a camera, and a

Serv_soc ⭐ 14

SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.

Riscv Atom ⭐ 14

An open-source 32-bit RISC-V soft-core processor for FPGAs.

De1 Soc Sound ⭐ 14

Mostly AVR compatible FPGA soft-core

Bitmips2019 ⭐ 13

Soc Lm32 ⭐ 12

Open source/hardware SoC plattform based on the lattice mico 32 softcore

Digital Hardware Modelling ⭐ 11

Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

Milkymist Mmu ⭐ 11

Milkymist MMU project

Md5cracker ⭐ 10

A Hardware MD5 Cracker for the Cyclone V SoC

Next186_soc_pc ⭐ 10

Riscv_soc ⭐ 10

Basic RISC-V Test SoC

Picorv32_eg4s20 ⭐ 10

A 32-bit RISC-V SoC on FPGA that supports RT-Thread.

ECE385 lab from UIUC

SoC based on RISC V ISA

Arm Cortex-M0 based Customizable SoC for IoT Applications

Xulalx25soc ⭐ 9

A System on a Chip Implementation for the XuLA2-LX25 board

Glitchhammer ⭐ 8

A custom coprocessor and SoC for hardware security experiments in electronics.

Soc_automation ⭐ 8

SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.

Amba_axi_ahb_apb ⭐ 8

AMBA bus lecture material

This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.

Sd_device ⭐ 8

SD device emulator from ProjectVault

Rocket Chip ⭐ 8

Openxc7 Tetrisaraj ⭐ 7

Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.

De10 Nano Riscv ⭐ 7

A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano

Barebonescortexm0 ⭐ 7

Extremely basic CortexM0 SoC based on ARM DesignStart Eval

Mips32r1_soc_nano ⭐ 7

A MIPS32 System-on-Chip for the DE0-Nano FPGA

Picorv32 SoC on the TinyFPGA BX, for games etc.

De1soc_media ⭐ 5

DE1SoC VGA and Audio

Fpga_test_soc ⭐ 5

A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)

Digilent Nexys2 port of the soc-lm32

A Framework for Prototyping of IoT Devices with High Level Synthesis Tools and SoC

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1-77 of 77 search results

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