Caravel
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Silice | 1,199 | 3 months ago | 73 | other | C++ | |||||
| Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures. | ||||||||||
| Caravel | 223 | 3 months ago | 100 | apache-2.0 | Verilog | |||||
| Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space. | ||||||||||
| Multiplier16x16 | 30 | 11 years ago | Verilog | |||||||
| Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder | ||||||||||
| Opensketch | 23 | 11 years ago | Verilog | |||||||
| simulation and netfpga code | ||||||||||
| Pyverilog_toolbox | 17 | 6 years ago | 7 | May 25, 2018 | apache-2.0 | Python | ||||
| Ece241_verilog | 7 | 3 years ago | 1 | gpl-3.0 | Verilog | |||||
| This repo contains all the Verilog HDL files that I made during the course. | ||||||||||
| Ice40_power | 7 | 4 years ago | mit | Verilog | ||||||
| Power analysis of the ICE40UP5K-SG48 devices | ||||||||||
| Mandelbrot | 6 | 2 years ago | Verilog | |||||||
| A Verilog based Fractal Set Generator for the Xilinx Artix 7 | ||||||||||
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