| sylefeb/Silice |
1,199 |
|
0 |
0 |
over 2 years ago |
0 |
|
73 |
other |
C++ |
| Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures. |
| efabless/caravel |
223 |
|
0 |
0 |
over 2 years ago |
0 |
|
100 |
apache-2.0 |
Verilog |
| Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space. |
| wuzeyou/Multiplier16X16 |
30 |
|
0 |
0 |
over 13 years ago |
0 |
|
0 |
|
Verilog |
| Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder |
| harvard-cns/opensketch |
23 |
|
0 |
0 |
about 13 years ago |
0 |
|
0 |
|
Verilog |
| simulation and netfpga code |
| tinyvision-ai-inc/ice40_power |
7 |
|
0 |
0 |
over 5 years ago |
0 |
|
0 |
mit |
Verilog |
| Power analysis of the ICE40UP5K-SG48 devices |
| pandyah5/ECE241_Verilog |
7 |
|
0 |
0 |
over 5 years ago |
0 |
|
1 |
gpl-3.0 |
Verilog |
| This repo contains all the Verilog HDL files that I made during the course. |
| mesarcik/MANDELBROT |
6 |
|
0 |
0 |
over 4 years ago |
0 |
|
0 |
|
Verilog |
| A Verilog based Fractal Set Generator for the Xilinx Artix 7 |
