Zbc The Zero Board Computer
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Wb2axip | 409 | 3 months ago | 3 | Verilog | ||||||
| Bus bridges and other odds and ends | ||||||||||
| Cores | 302 | 3 years ago | 3 | Verilog | ||||||
| Various HDL (Verilog) IP Cores | ||||||||||
| Opdb | 18 | a year ago | Verilog | |||||||
| OpenPiton Design Benchmark | ||||||||||
| Polaris | 16 | 7 years ago | 5 | mpl-2.0 | Verilog | |||||
| RISC-V RV64IS-compatible processor for the Kestrel-3 | ||||||||||
| Zbc The Zero Board Computer | 15 | 4 years ago | 1 | gpl-3.0 | Verilog | |||||
| Based heavily on zet.aluzina.org and Terasic DE0 | ||||||||||
| Core_dbg_bridge | 12 | 3 years ago | lgpl-2.1 | Verilog | ||||||
| UART -> AXI Bridge | ||||||||||
| Core_usb_bridge | 11 | 3 years ago | lgpl-2.1 | Verilog | ||||||
| USB -> AXI Debug Bridge | ||||||||||
| Jtag_dpi | 9 | 12 years ago | C++ | |||||||
| JTAG DPI module for OpenRISC simulation with Verilator | ||||||||||
| Fpdpga | 5 | 3 years ago | 1 | mit | Verilog | |||||
| FPGA implementations of the PDP-6 and PDP-10 | ||||||||||
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