Xilinx_axidma
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Uhd | 869 | 3 | 4 months ago | 11 | September 14, 2022 | 93 | other | Verilog | ||
| The USRP™ Hardware Driver Repository | ||||||||||
| No Os | 816 | 3 months ago | 10 | other | C | |||||
| Software drivers in C for systems without an operating system | ||||||||||
| Xilinx_axidma | 194 | 4 years ago | 41 | mit | C | |||||
| A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License. | ||||||||||
| Softmc | 103 | 8 months ago | 1 | mit | Verilog | |||||
| SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" <https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17.pdf> | ||||||||||
| Zynq Xdma | 60 | 9 years ago | 5 | C | ||||||
| Linux Driver for the Zynq FPGA DMA engine | ||||||||||
| Images | 37 | 2 years ago | 50 | CMake | ||||||
| Pre-built XTRX packages and firmware images | ||||||||||
| Pcie Fpga | 33 | 10 years ago | mit | C | ||||||
| Linux kernel driver for memory mapped PCIe - FPGA communication. | ||||||||||
| Bar Tender | 30 | 6 years ago | 1 | mit | Verilog | |||||
| An FPGA I/O Device which services physical memory reads/writes via UMDF2 driver | ||||||||||
| Fclkcfg | 21 | 10 months ago | 1 | bsd-2-clause | C | |||||
| FPGA Clock Configuration Device Driver for Linux | ||||||||||
| Rosetta | 21 | 6 years ago | bsd-2-clause | Tcl | ||||||
| Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ | ||||||||||
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