Hls_tutorial_examples

Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
Alternatives To Hls_tutorial_examples
Project NameStarsDownloadsRepos Using ThisPackages Using ThisMost Recent CommitTotal ReleasesLatest ReleaseOpen IssuesLicenseLanguage
Vtr Verilog To Routing925
3 months ago447otherC++
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Edalize573233 months ago24December 08, 202391bsd-2-clausePython
An abstraction library for interfacing EDA tools
Pipelinec519
3 months ago82gpl-3.0Python
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Leflow329
4 years ago1otherVerilog
Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
Poc324
4 years ago31otherVHDL
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
F4pga Arch Defs245
a month ago366iscJupyter Notebook
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Livehd192
3 months ago4June 06, 201811otherVerilog
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
Panda Bambu192
3 months ago8gpl-3.0C++
PandA-bambu public repository
Async_fifo173
a year agootherVerilog
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Logic121
4 years agoapache-2.0SystemVerilog
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Alternatives To Hls_tutorial_examples
Select To Compare


Alternative Project Comparisons
Popular Synthesis Projects
Popular Fpga Projects
Popular Media Categories
Related Searches

Get A Weekly Email With Trending Projects For These Categories
No Spam. Unsubscribe easily at any time.
C Plus Plus
Intel
Fpga
Synthesis
Opencl
Hls