Ucr Eecs168 Lab
The lab schedules for EECS168 at UC Riverside
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Openfpga | 692 | 3 months ago | 103 | mit | Verilog | |||||
| An Open-source FPGA IP Generator | ||||||||||
| Ucr Eecs168 Lab | 423 | a year ago | 70 | Verilog | ||||||
| The lab schedules for EECS168 at UC Riverside | ||||||||||
| Awesome Fpga | 150 | 7 years ago | gpl-3.0 | |||||||
| A collection of resources on FPGA devices and development in general | ||||||||||
| Pymtl | 149 | 4 years ago | 81 | bsd-3-clause | Python | |||||
| Python-based hardware modeling framework | ||||||||||
| Fpgamake | 78 | 2 years ago | 2 | Tcl | ||||||
| Generates Makefiles to synthesize, place, and route verilog using Vivado | ||||||||||
| Nscscc Wiki | 60 | 3 years ago | ||||||||
| NSCSCC 信息整合 | ||||||||||
| Chiphack | 43 | 6 years ago | 2 | other | Verilog | |||||
| Repository and Wiki for Chip Hack events. | ||||||||||
| Openfpga Tutorials | 26 | 6 months ago | mit | |||||||
| A collection of tutorials and resources for the openFPGA platform. | ||||||||||
| Verilog_tutorials_bb | 16 | 8 years ago | Verilog | |||||||
| verilog tutorials for iCE40HX8K Breakout Board | ||||||||||
| Website | 13 | 3 months ago | HTML | |||||||
| The ZipCPU blog | ||||||||||
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