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Search results for verilog

2,185 search results found

Scamp Cpu ⭐ 279

A homebrew 16-bit CPU with a homebrew Unix-like-ish operating system.

Verilog Uart ⭐ 277

Veriloggen ⭐ 275

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

Step_into_mips ⭐ 271

一步一步写MIPS CPU

Fpga Imaging Library ⭐ 271

An open source library for image processing on FPGA.

Vscode Verilog Hdl Support ⭐ 266

HDL support for VS Code

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

Code generation tool for configuration and status registers

Ustc Rvsoc ⭐ 261

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Nuked Md Fpga ⭐ 259

Mega Drive/Genesis core written in Verilog

Hdlconvertor ⭐ 258

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

synthesiseable ieee 754 floating point library in verilog

Sv Tests ⭐ 257

Test suite designed to check compliance with the SystemVerilog standard.

Hardware implementation of the SHA-256 cryptographic hash function

SystemVerilog linter

Volumetric Display using an Acoustically Trapped Particle

Openofdm ⭐ 251

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

Project Zipline ⭐ 251

Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.

Netfpga ⭐ 250

NetFPGA 1G infrastructure and gateware

Fpga_readings ⭐ 249

Recipe for FPGA cooking

F4pga Arch Defs ⭐ 248

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Nestang ⭐ 245

NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards

Verilog ⭐ 243

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Fpga Usb Device ⭐ 241

An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Wbuart32 ⭐ 237

A simple, basic, formally verified UART controller

Openroad Flow Scripts ⭐ 233

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/la

F4pga Examples ⭐ 232

Example designs showing different ways to use F4PGA toolchains.

Verilog Generator Of Neural Net Digit Detector For Fpga ⭐ 231

Verilog Generator of Neural Net Digit Detector for FPGA

Verilog Mode ⭐ 231

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

Fpga Litecoin Miner ⭐ 231

A litecoin scrypt miner implemented with FPGA on-chip memory.

Piccolo ⭐ 227

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

Veryl: A Modern Hardware Description Language

Ice40 Playground ⭐ 224

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

Ao486_mister ⭐ 223

ao486 port for MiSTer

Caravel ⭐ 223

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

Analogue_pocket_neogeo ⭐ 220

Analogue Pocket Neogeo Core compatible with openFPGA

Openc906 ⭐ 218

OpenXuantie - OpenC906 Core

Ip Cores ⭐ 214

A huge collection of VHDL/Verilog open-source IP cores scraped from the web

A modern and open-source cross-platform software for chips reverse engineering.

Chips 2.0 ⭐ 205

FPGA Design Suite based on C to Verilog design flow.

Open source implementation of a x86 processor

Colorlight Fpga Projects ⭐ 196

current focus on Colorlight i5 and i9 & i9plus module

Dblclockfft ⭐ 195

A configurable C++ generator of pipelined Verilog FFT cores

An HDL embedded in Rust.

The USRP™ Hardware Driver FPGA Repository

Scale Mamba ⭐ 189

Repository for the SCALE-MAMBA MPC system

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Convolution_network_on_fpga ⭐ 187

CNN acceleration on virtex-7 FPGA with verilog HDL

An open source SPI flash emulator and monitor

The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.

Ridecore ⭐ 185

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

Minimax ⭐ 180

Minimax: a Compressed-First, Microcoded RISC-V CPU

A Compiler for the Popr Language

Fpga Ftdi245fifo ⭐ 178

FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

Libsystemctlm Soc ⭐ 175

SystemC/TLM-2.0 Co-simulation framework

Riscv Bitmanip ⭐ 174

Working draft of the proposed RISC-V Bitmanipulation extension

Fpga_nes ⭐ 173

FPGA-based Nintendo Entertainment System Emulator

Async_fifo ⭐ 173

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Awesome Scs ⭐ 172

上海交通大学网安学院本科编程作业参考

Amiga_replacement_project ⭐ 171

This is an attempt to make clean Verilog sources for each chip on the Amiga.

Kestrel ⭐ 171

The Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.

Open Register Design Tool ⭐ 169

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Fpga Chip8 ⭐ 167

CHIP-8 console on FPGA

FPGA implementation of DEC PDP-1 computer (1959) in Verilog, with CRT, Teletype and Console.

Zynq Nvdla ⭐ 165

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

Qflow full end-to-end digital synthesis flow for ASIC designs

xk265：HEVC/H.265 Video Encoder IP Core (RTL)

Eurorack Pmod ⭐ 160

A eurorack-friendly audio frontend compatible with many FPGA boards.

Tinyfpga B Series ⭐ 160

Open source design files for the TinyFPGA B-Series boards.

Twitchcore ⭐ 158

It's a core. Made on Twitch.

Vicii Kawari ⭐ 157

Commodore 64 VIC-II 6567/6569 Replacement Project

Connectal ⭐ 153

Connectal is a framework for software-driven hardware development.

Autofpga ⭐ 153

A utility for Composing FPGA designs from Peripherals

Caravel_user_project ⭐ 152

https://caravel-user-project.readthedocs.io

Open source software for chip reverse engineering.

Detecthumanfaces ⭐ 151

Real time face detection based on Arm Cortex-M3 DesignStart and FPGA

Awesome Fpga ⭐ 150

A collection of resources on FPGA devices and development in general

Fpga Peripherals ⭐ 149

🌱 ❄️ Collection of open-source peripherals in Verilog

Verilog Format ⭐ 149

Verilog formatter

Python-based hardware modeling framework

Fomu Workshop ⭐ 148

Support files for participating in a Fomu workshop

Fpgaandcnn ⭐ 148

基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现

Zx Sizif 512 ⭐ 148

ZX Spectrum CPLD-based clone for rubber case

Usbcorev ⭐ 146

A full-speed device-side USB peripheral core written in Verilog.

A C++ to Verilog translation tool with some basic guarantees that your code will work.

Icegdrom ⭐ 142

An FPGA based GDROM emulator for the Sega Dreamcast

Fpga Sdcard Reader ⭐ 142

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

Revengineered ancient PDP-11 CPUs, originals and clones

Verilogcreator ⭐ 141

VerilogCreator is a QtCreator based IDE for Verilog 2005

Fpga Jpeg Ls Encoder ⭐ 141

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

Single_instruction_cycle_openmips ⭐ 139

通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五

Hdmi2usb Litex Firmware ⭐ 139

A version of the HDMI2USB firmware based around LiteX tools produced by @Enjoy-Digital (based on misoc+migen created by @M-Labs)

Nintendo Entertainment System (NES) / Famicom / Famiclones chip reversing

De10 Nano ⭐ 137

Absolute beginner's guide to the de10-nano

Hdl_checker ⭐ 136

Repurposing existing HDL tools to help writing better code

Openfpgaduino ⭐ 135

All open source file and project for OpenFPGAduino project

Open5g_phy ⭐ 135

A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog

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