Awesome Scs
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Fpga Litecoin Miner | 231 | 10 years ago | 6 | gpl-3.0 | Verilog | |||||
| A litecoin scrypt miner implemented with FPGA on-chip memory. | ||||||||||
| Awesome Scs | 172 | a year ago | 2 | mit | ||||||
| 上海交通大学网安学院本科编程作业参考 | ||||||||||
| Xilinx Serial Miner | 75 | 11 years ago | 1 | gpl-3.0 | Verilog | |||||
| Bitcoin miner for Xilinx FPGAs | ||||||||||
| Systemverilogsha256 | 34 | 6 years ago | gpl-3.0 | SystemVerilog | ||||||
| SHA256 in (System-) Verilog / Open Source FPGA Miner | ||||||||||
| Mm | 24 | 7 years ago | 7 | unlicense | Verilog | |||||
| Miner Manager | ||||||||||
| Awesome Hdl | 14 | 8 years ago | 1 | other | ||||||
| A curated list of awesome HDL, libraries, typical implementation and references. | ||||||||||
| Shapool Core | 13 | 3 years ago | 6 | bsd-3-clause | Verilog | |||||
| FPGA core for SHA256d mining targeting Lattice iCE40 devices. | ||||||||||
| Verilogsha256miner | 8 | 6 years ago | Verilog | |||||||
| Implementation of SHA256 Hasher with UART Transceiver in Verilog. Designed to run on Altera's DE2 FPGA Development Board. | ||||||||||
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