Awesome Open Source
Search
Programming Languages
Languages
All Categories
Categories
About
Search results for verilog synthesis
synthesis
x
verilog
x
71 search results found
Hw
⭐
1,254
RTL, Cmodel, and testbench for NVDLA
Xls
⭐
1,087
XLS: Accelerated HW Synthesis
Vtr Verilog To Routing
⭐
925
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Awesome Hdl
⭐
830
Hardware Description Languages
Minecrafthdl
⭐
595
A Verilog synthesis flow for Minecraft redstone circuits
Edalize
⭐
573
An abstraction library for interfacing EDA tools
Leflow
⭐
329
Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
Nngen
⭐
281
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
Veriloggen
⭐
275
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
Project Zipline
⭐
251
Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.
Netfpga
⭐
250
NetFPGA 1G infrastructure and gateware
F4pga Arch Defs
⭐
245
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Async_fifo
⭐
173
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Qflow
⭐
164
Qflow full end-to-end digital synthesis flow for ASIC designs
Logic
⭐
121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Tinygarble
⭐
113
TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits
Verismith
⭐
89
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
Karuta
⭐
87
Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.
Shang
⭐
85
The Shang high-level synthesis framework
Circuitgraph
⭐
74
Tools for working with circuits as graphs in python
Vericert
⭐
73
A formally verified high-level synthesis tool based on CompCert and written in Coq.
Rt
⭐
71
A Full Hardware Real-Time Ray-Tracer
Systemc Clang
⭐
59
This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
Riscv Simple Sv
⭐
56
A simple RISC V core for teaching
Pycoram
⭐
42
Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
Autopiper
⭐
40
Xpm_vhdl
⭐
38
A translation of the Xilinx XPM library to VHDL for simulation purposes
Docker
⭐
34
Scripts to build and use docker images including GHDL
Dcpu16
⭐
34
Pipelined DCPU-16 Verilog Implementation
Frix
⭐
32
IBM PC Compatible SoC for a commercially available FPGA board
Xeda
⭐
30
Cross EDA Abstraction and Automation
Manthan
⭐
26
Manthan for Boolean function synthesis
Yosys Bigsim
⭐
24
A collection of big designs to run post-synthesis simulations with yosys
My Verilog Examples
⭐
22
A place to keep my synthesizable verilog examples.
Edif2qmasm
⭐
21
Run hardware descriptions on a quantum annealer
Blasys
⭐
21
An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
Design And Asic Implementation Of 32 Point Fft Processor
⭐
20
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of a
Hwthls
⭐
20
LLVM based HLS library for HWToolkit (hardware devel. toolkit)
Vloghammer
⭐
19
A Verilog Synthesis Regression Test
Svinst
⭐
18
Determines the modules declared and instantiated in a SystemVerilog file
Hardware
⭐
18
Verilog development and verification project for HOL4
Picoblaze Library
⭐
18
The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).
Datc_robust_design_flow
⭐
15
DATC Robust Design Flow.
X393_sata
⭐
15
mirror of https://git.elphel.com/Elphel/x393_sata
Tiny Tpu
⭐
14
Small-scale Tensor Processing Unit built on an FPGA
Asynchronous Verilog Synthesiser
⭐
14
Synthesiser for Asynchronous Verilog Language
Idea
⭐
14
Rdf 2019
⭐
14
DATC RDF
Yosys Tcl Ui Report
⭐
12
5 Day TCL begginer to advanced training workshop by VSD
Svreal
⭐
11
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
C Ll Verilog
⭐
10
An LLVM based mini-C to Verilog High-level Synthesis tool
Regal
⭐
10
A set of scripts used to assist reverse engineering of old-school Programmable Array Logic devices.
Oc I2c
⭐
10
I2C controller core from Opencores.org
Hls_ldpc_dec
⭐
9
Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..
Awesome Eda
⭐
9
S Link
⭐
8
An Open Source Link Protocol and Controller
Yosys Bluespec
⭐
8
Yosys plugin for synthesis of Bluespec code
Pymtl Tut Hls
⭐
8
Tutorial for integrating PyMTL and Vivado HLS
Bwa Mem Sw
⭐
8
Pysvinst
⭐
8
Python library for parsing module definitions and instantiations from SystemVerilog files
Multiported Ram
⭐
8
Modular Multi-ported SRAM-based Memory
Axicores
⭐
8
AXI4-Compatible Verilog Cores, along with some helper modules.
Rc4 Prbs
⭐
7
A Verilog open-source implementation of a RC4 encryption algorigthm using a pseudorandom binary sequence (PRBS) for FPGA synthesis.
Alogic
⭐
6
Alogic is a Medium Level Synthesis language for digital logic that compiles swiftly into standard Verilog-2005 for implementation in ASIC or FPGA.
Ncore
⭐
6
A RISCV processor in system verilog
Gost 28147 89
⭐
5
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
Digilite_zl
⭐
5
DigiLiteZL FPGA
Microcoder
⭐
5
Define custom assembly-like instructions and use them to write programs which are transpiled into synthesisable Verilog code.
Interleaved Synthesizable Synchronization Fifos
⭐
5
Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs
Pyjer
⭐
5
A Framework for Prototyping of IoT Devices with High Level Synthesis Tools and SoC
Pulsar
⭐
5
Pulsar asynchronous synthesis framework
Related Searches
Verilog Fpga (1,343)
Python Synthesis (769)
Cpu Verilog (330)
C Plus Plus Synthesis (305)
Python Verilog (267)
Verilog Xilinx (265)
Verilog Vhdl (249)
Verilog Systemverilog (230)
Verilog Rtl (217)
C Plus Plus Verilog (187)
1-71 of 71 search results
Privacy
|
About
|
Terms
|
Follow Us On Twitter
Copyright 2018-2024 Awesome Open Source. All rights reserved.