Hardware
Verilog development and verification project for HOL4
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Hw | 1,254 | 2 years ago | 193 | other | Verilog | |||||
| RTL, Cmodel, and testbench for NVDLA | ||||||||||
| Xls | 1,087 | 3 months ago | 607 | apache-2.0 | C++ | |||||
| XLS: Accelerated HW Synthesis | ||||||||||
| Vtr Verilog To Routing | 925 | 3 months ago | 447 | other | C++ | |||||
| Verilog to Routing -- Open Source CAD Flow for FPGA Research | ||||||||||
| Awesome Hdl | 830 | 3 months ago | 1 | |||||||
| Hardware Description Languages | ||||||||||
| Minecrafthdl | 595 | 3 years ago | 7 | SystemVerilog | ||||||
| A Verilog synthesis flow for Minecraft redstone circuits | ||||||||||
| Edalize | 573 |  | 2 | 3 | 3 months ago | 24 | December 08, 2023 | 91 | bsd-2-clause | Python |
| An abstraction library for interfacing EDA tools | ||||||||||
| Leflow | 329 | 4 years ago | 1 | other | Verilog | |||||
| Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks | ||||||||||
| Nngen | 281 | 6 months ago | 5 | September 12, 2023 | 31 | apache-2.0 | Python | |||
| NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network | ||||||||||
| Veriloggen | 275 | 1 | 7 months ago | 75 | September 12, 2023 | 19 | apache-2.0 | Python | ||
| Veriloggen: A Mixed-Paradigm Hardware Construction Framework | ||||||||||
| Project Zipline | 251 | 3 years ago | 8 | other | Verilog | |||||
| Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm. | ||||||||||
Alternatives To HardwareSelect To Compare
Alternative Project Comparisons
Popular Verilog Projects
Popular Synthesis Projects
Popular Hardware Categories
Related Searches
Get A Weekly Email With Trending Projects For These Categories
No Spam. Unsubscribe easily at any time.
Verilog
Synthesis
Ag
Formal Methods