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Search results for verilog verilator
verilator
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verilog
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40 search results found
Verilator
⭐
1,934
Verilator open-source SystemVerilog simulator and lint system
Zipcpu
⭐
1,139
A small, light weight, RISC CPU soft core
Edalize
⭐
573
An abstraction library for interfacing EDA tools
Riscv
⭐
364
RISC-V CPU Core (RV32IM)
Cores
⭐
302
Various HDL (Verilog) IP Cores
Biriscv
⭐
300
32-bit Superscalar RISC-V CPU
Vscode Verilog Hdl Support
⭐
266
HDL support for VS Code
Wbuart32
⭐
237
A simple, basic, formally verified UART controller
Dblclockfft
⭐
195
A configurable C++ generator of pipelined Verilog FFT cores
Async_fifo
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173
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Autofpga
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153
A utility for Composing FPGA designs from Peripherals
Vgasim
⭐
124
A Video display simulator
Logic
⭐
121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Sdspi
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91
SD-Card controller, using a SPI interface that is (optionally) shared
Dpll
⭐
82
A collection of phase locked loop (PLL) related projects
Openarty
⭐
77
An Open Source configuration of the Arty platform
Wbscope
⭐
67
A wishbone controlled scope for FPGA's
Fakepga
⭐
66
Simulating Verilog designs on a microcontroller
Hdl Tools
⭐
60
Facilitates building open source tools for working with hardware description languages (HDLs)
Svut
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59
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
Interpolation
⭐
42
Digital Interpolation Techniques Applied to Digital Signal Processing
Wbi2c
⭐
35
Wishbone controlled I2C controllers
Zbasic
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35
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
Vboard
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34
Virtual development board for HDL design
Dbgbus
⭐
31
A collection of debugging busses developed and presented at zipcpu.com
S6soc
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24
CMod-S6 SoC
Scarv Cpu
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18
SCARV: a side-channel hardened RISC-V platform
Virtio
⭐
18
Virtio implementation in SystemVerilog
Rules_verilator
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16
Bazel build rules for Verilator
Sublimelinter Contrib Verilator
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13
👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)
Website
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13
The ZipCPU blog
Nirah
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11
Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.
Svreal
⭐
11
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
Croyde Riscv
⭐
10
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
Verilator Project Template
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10
Template Verilator project for beginners
Riscv
⭐
8
32-bit soft RISCV processor for FPGA applications
Pci Edu
⭐
6
SystemVerilog implemention of QEMU PCI edu device
Linter Veriloghdl
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6
Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.
Go.debug
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5
Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster
Gvi
⭐
5
GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
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