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Search results for verilator
verilator
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53 search results found
Verilator
⭐
1,934
Verilator open-source SystemVerilog simulator and lint system
Zipcpu
⭐
1,139
A small, light weight, RISC CPU soft core
Cores Veer Eh1
⭐
770
VeeR EH1 core
Edalize
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573
An abstraction library for interfacing EDA tools
Riscv
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364
RISC-V CPU Core (RV32IM)
Cores
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302
Various HDL (Verilog) IP Cores
Biriscv
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300
32-bit Superscalar RISC-V CPU
Vscode Verilog Hdl Support
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266
HDL support for VS Code
Wbuart32
⭐
237
A simple, basic, formally verified UART controller
Cores Veer El2
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222
VeeR EL2 Core
Dblclockfft
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195
A configurable C++ generator of pipelined Verilog FFT cores
Async_fifo
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173
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Autofpga
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153
A utility for Composing FPGA designs from Peripherals
Vgasim
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124
A Video display simulator
Logic
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121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Sdspi
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91
SD-Card controller, using a SPI interface that is (optionally) shared
Dpll
⭐
82
A collection of phase locked loop (PLL) related projects
Openarty
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77
An Open Source configuration of the Arty platform
Wbscope
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67
A wishbone controlled scope for FPGA's
Fakepga
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66
Simulating Verilog designs on a microcontroller
Hdl Tools
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60
Facilitates building open source tools for working with hardware description languages (HDLs)
Svut
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59
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
Interpolation
⭐
42
Digital Interpolation Techniques Applied to Digital Signal Processing
Zbasic
⭐
35
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
Wbi2c
⭐
35
Wishbone controlled I2C controllers
Vboard
⭐
34
Virtual development board for HDL design
Dbgbus
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31
A collection of debugging busses developed and presented at zipcpu.com
Tree Core Cpu
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29
A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
S6soc
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24
CMod-S6 SoC
Eda_tools
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24
A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.
Scarv Cpu
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18
SCARV: a side-channel hardened RISC-V platform
Virtio
⭐
18
Virtio implementation in SystemVerilog
Rules_verilator
⭐
16
Bazel build rules for Verilator
Quasar
⭐
13
Quasar 2.0: Chisel equivalent of SweRV-EL2
Website
⭐
13
The ZipCPU blog
Sublimelinter Contrib Verilator
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13
👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)
Verilator_ext_tests
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12
Extended and external tests for Verilator testing
Svreal
⭐
11
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
Ics 2021spring Fdu
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11
Introduction to Computer Systems (II), Spring 2021.
Nirah
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11
Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.
Verilator Project Template
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10
Template Verilator project for beginners
Croyde Riscv
⭐
10
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
Verifying Foss Hdl Synthesizers
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10
a project to check the FOSS synthesizers against vendors EDA tools
Noop Lo
⭐
9
A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
Vrtlmod
⭐
9
vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/Clang-Tools and generates a fault injection API.
Riscv
⭐
8
32-bit soft RISCV processor for FPGA applications
My Riscv64 Core Writing
⭐
6
一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .
Bossa
⭐
6
BOOM's Simulation Accelerator.
Vga_interface
⭐
6
Linter Veriloghdl
⭐
6
Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.
Pci Edu
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6
SystemVerilog implemention of QEMU PCI edu device
Gvi
⭐
5
GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
Go.debug
⭐
5
Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster
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1-53 of 53 search results
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