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Search results for verilog

2,185 search results found

Fedar F1 Rv64im ⭐ 84

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

A core language for rule-based hardware design 🦑

uvm AXI BFM(bus functional model)

Fpga Ddr Sdram ⭐ 83

An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

Vt52 Fpga ⭐ 83

Bottlerocket ⭐ 83

A collection of phase locked loop (PLL) related projects

Yosys F4pga Plugins ⭐ 81

Plugins for Yosys developed as part of the F4PGA project.

XCrypto: a cryptographic ISE for RISC-V

Cnn_for_slr ⭐ 79

A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.

Fpga Rocket Chip ⭐ 79

Wrapper for Rocket-Chip on FPGAs

Neogeohdmi ⭐ 79

Verilog project that takes the digital video and audio from a Neo Geo MVS before going through the DACs and outputs the signals over HDMI

Fpgamake ⭐ 78

Generates Makefiles to synthesize, place, and route verilog using Vivado

Lpc_sniffer_tpm ⭐ 77

A low pin count sniffer for ICEStick - targeting TPM chips

Openarty ⭐ 77

An Open Source configuration of the Arty platform

Homotopy ⭐ 76

Homotopy theory in Coq.

The second place winner for DAC-SDC 2020

Limesdr Usb_gw ⭐ 76

Altera Cyclone IV FPGA project for the USB 3.0 LimeSDR board

Fpga Cnn ⭐ 76

FPGA implementation of Cellular Neural Network (CNN)

2021_spring_nctu_iclab ⭐ 76

NCTU 2021 Spring Integrated Circuit Design Laboratory

Awesome Dv ⭐ 76

Awesome ASIC design verification

Usb_hid_host ⭐ 76

A compact USB HID host FPGA core supporting keyboards, mice and gamepads.

Yet Another RISC-V Implementation

Xilinx Serial Miner ⭐ 75

Bitcoin miner for Xilinx FPGAs

Verilog Fixedpoint ⭐ 75

A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

Pixel Wrangler ⭐ 75

HDMI to whatever adapter

Lattice iCE40 FPGA experiments - Work in progress

Mipsfpga Plus ⭐ 74

MIPSfpga+ allows loading programs via UART and has a switchable clock

Projectoberon2013 ⭐ 74

Project Oberon (New Edition 2013) Unofficial Mirror

Gottagofastram ⭐ 74

8MB Autoconfig FastRAM for Amiga 500/1000/2000/CDTV

YM2151 clone in verilog. FPGA proven.

Circuitgraph ⭐ 74

Tools for working with circuits as graphs in python

Vericert ⭐ 73

A formally verified high-level synthesis tool based on CompCert and written in Coq.

Sd Card Controller ⭐ 73

WISHBONE SD Card Controller IP Core

Implementation Nintendo's GameBoy console on an FPGA

Mips32 Cpu ⭐ 73

奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）

Fpga Nfc ⭐ 73

Build an NFC (RFID) card reader using FPGA and simple circuit instead of RFID-specfic chip. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器，不需要专门的RFID芯片。

Symbolator ⭐ 73

HDL symbol generator

A very primitive but hopefully self-educational CPU in Verilog

A reimplementation of a tiny stack CPU

Keyboard ⭐ 72

客制化机械键盘——从0开始全套资料

LatticeMico32 soft processor

A Full Hardware Real-Time Ray-Tracer

Tree Sitter Verilog ⭐ 70

SystemVerilog grammar for tree-sitter

Analogue Amiga ⭐ 69

Core_ddr3_controller ⭐ 69

A DDR3 memory controller in Verilog for various FPGAs

Fpga Sdfake ⭐ 69

Imitate SDcard using FPGAs. 使用FPGA模拟(伪装) SD卡。

Simbricks ⭐ 69

Main Repository for the SimBricks Modular Full-System Simulation Framework.

A series of CORDIC related projects

👾 Design ∪ Hardware

Ice40linux ⭐ 68

Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker

Verilog Parser ⭐ 68

A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.

A wishbone controlled scope for FPGA's

Open Nic Shell ⭐ 67

AMD OpenNIC Shell includes the HDL source files

Filament ⭐ 66

Fearless hardware design

Spydrnet ⭐ 66

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Systemctlm Cosim Demo ⭐ 66

Simulating Verilog designs on a microcontroller

Learning how to make a RISC-V

Core Template ⭐ 66

A template for getting started with FPGA core development

C5soc_opencl ⭐ 65

DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.

FPGA Based Apollo Guidance Computer

Antikernel ⭐ 65

The Antikernel operating system project

D3 Hwschematic ⭐ 64

D3.js and ELK based schematic visualizer

Display_controller ⭐ 64

FPGA display controller with support for VGA, DVI, and HDMI.

浙江大学计算机体系结构课程实验

Template_mister ⭐ 64

Template with latest framework for MiSTer

Megacd_mister ⭐ 63

Mega CD for MiSTer

Tinyfpga_bx_usbserial ⭐ 63

USB Serial on the TinyFPGA BX

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

Ponylink ⭐ 63

A single-wire bi-directional chip-to-chip interface for FPGAs

Naivemips Hdl ⭐ 63

Naïve MIPS32 SoC implementation

3-stage RV32IMACZb* processor with debug

Parallel Array of Simple Cores. Multicore processor.

Sega System For Fpga ⭐ 61

FPGA Sega in Verilog, for Xilinx Virtex, circa 2002. Has an emulator thrown in, to simplify FPGA debugging.

FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器，用来进行无损图像压缩。

Zynq Axis ⭐ 61

Hardware, Linux Driver and Library for the Zynq AXI DMA interface

Arduino compatible – Cortex M4F & FPGA Development Board

Hdl Tools ⭐ 61

Facilitates building open source tools for working with hardware description languages (HDLs)

Nscscc Wiki ⭐ 60

NSCSCC 信息整合

Cnn_open ⭐ 60

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Systemc Clang ⭐ 59

This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.

Sv2chisel ⭐ 59

(System)Verilog to Chisel translator

Verilog Wishbone ⭐ 59

Verilog wishbone components

Common framework for MiST(er), PocketFPGA, SiDi, NeptUNO (mc/mc2) core development. With special focus on arcade cores.

A crazy small 8-bit CPU built with only seventeen 7400-series chips.

Oc Accel ⭐ 58

OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology

Fpga Odysseus ⭐ 58

FPGA Odysseus with ULX3S

Fpga Png Decoder ⭐ 57

An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图象解码器，可以从PNG文件中解码出原始像素。

Bch_verilog ⭐ 57

Verilog based BCH encoder/decoder

⚔️ Debuggable hardware generator

Aib Phy Hardware ⭐ 57

Verilog 65c02 Microcode ⭐ 57

65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface

Sol-1: A CPU/Computer System made from 74 series logic.

open-source logic analyzer for FPGAs

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301-400 of 2,185 search results

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