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Search results for verilog hls

25 search results found

Openwifi ⭐ 3,363

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Basic_verilog ⭐ 1,333

Must-have verilog systemverilog modules

XLS: Accelerated HW Synthesis

Awesome Hdl ⭐ 830

Hardware Description Languages

Openwifi Hw ⭐ 560

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Fpga_readings ⭐ 249

Recipe for FPGA cooking

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

The second place winner for DAC-SDC 2020

Vericert ⭐ 73

A formally verified high-level synthesis tool based on CompCert and written in Coq.

Oc Accel ⭐ 58

OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology

hardware library for hwt (= ipcore repo)

Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)

Ml4accel Dataset ⭐ 20

Dataset for ML-guided Accelerator Design

LLVM based HLS library for HWToolkit (hardware devel. toolkit)

An infrastructure for inline acceleration of network applications

Ece1373_2016_hft_on_fpga ⭐ 16

High Frequency Trading using Vivado HLS

Digital Hardware Modelling ⭐ 11

Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

Aes_chisel ⭐ 10

Implementation of the Advanced Encryption Standard in Chisel

C Ll Verilog ⭐ 10

An LLVM based mini-C to Verilog High-level Synthesis tool

Hls_ldpc_dec ⭐ 9

Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..

Pymtl Tut Hls ⭐ 8

Tutorial for integrating PyMTL and Vivado HLS

Implementation of various projects on Cyclone V FPGA

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1-25 of 25 search results

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