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Search results for fpga hls
fpga
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hls
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96 search results found
Openwifi
⭐
3,363
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
Basic_verilog
⭐
1,333
Must-have verilog systemverilog modules
Hls4ml
⭐
1,104
Machine learning on FPGAs using HLS
Pipecnn
⭐
916
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
Nmigen
⭐
589
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
Openwifi Hw
⭐
560
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Fpga Network Stack
⭐
559
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
Pipelinec
⭐
519
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Zynqnet
⭐
510
Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"
Pp4fpgas Cn
⭐
394
中文版 Parallel Programming for FPGAs
Esp
⭐
267
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
Fpga_readings
⭐
249
Recipe for FPGA cooking
Hlslib
⭐
236
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
Panda Bambu
⭐
192
PandA-bambu public repository
Hwt
⭐
189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Gemm_hls
⭐
184
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
Scalehls
⭐
157
A scalable High-Level Synthesis framework on MLIR
Hls_tutorial_examples
⭐
107
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
Pp4fpgas Cn Hls
⭐
102
HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn
Thundergp
⭐
90
HLS-based Graph Processing Framework on FPGAs
Karuta
⭐
87
Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.
Rapidstream
⭐
85
[FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
Limago
⭐
83
Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
Autobridge
⭐
81
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
Autosa
⭐
80
AutoSA: Polyhedral-Based Systolic Array Compiler
Skrskr
⭐
76
The second place winner for DAC-SDC 2020
Skynet
⭐
75
Rfnoc Hls Neuralnet
⭐
61
Oc Accel
⭐
58
OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
Fpga Zynqnet
⭐
56
FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS
Vitis_model_composer
⭐
54
Vitis Model Composer Examples and Tutorials
Halide Hls
⭐
49
HLS branch of Halide
Flexcnn
⭐
47
Opennna
⭐
46
一个开源的FPGA神经网络加速器。
Ismartdnn
⭐
45
Light-weighted neural network inference for object detection on small-scale FPGA board
Ultra_net
⭐
43
FPGA-based neural network inference project for 2020 DAC System Design Contest
Fos
⭐
40
FOS - FPGA Operating System
Hwtlib
⭐
33
hardware library for hwt (= ipcore repo)
100g Fpga Network Stack Core
⭐
31
This repo contains the Limago code
Iroha
⭐
30
Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
Hlsclt
⭐
30
A Vivado HLS Command Line Helper Tool
Facedetect Fpga
⭐
29
Axorderbook
⭐
27
A股订单簿工具,使用逐笔行情进行订单簿重建、千档快照发布、各档委托队列展示等,包括python模型和 HLS实现。
Lutnet
⭐
21
Rosetta
⭐
21
Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
Hwthls
⭐
20
LLVM based HLS library for HWToolkit (hardware devel. toolkit)
Cnn_fpga_zynq_pynq
⭐
20
hls code zynq 7020 pynq z2 CNN
Fpga Dcnn Accelerator
⭐
19
基于HLS的高效深度卷积神经网络FPGA实现方法
Hls Cnn
⭐
19
High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
Rapidstream
⭐
19
[FPGA 2022] Parallel placement and routing of Vivado HLS dataflow designs.
Apfp
⭐
19
FPGA acceleration of arbitrary precision floating point computations.
Nica
⭐
18
An infrastructure for inline acceleration of network applications
Open Dnn
⭐
18
Elasticc
⭐
18
lightweight open HLS for FPGA rapid prototyping
Vivado Hls Broadcast Optimization
⭐
16
[DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
Rfnoc Hls Atsc Rx
⭐
16
Stereo Vision Fpga
⭐
15
Real-time binocular stereo vision FPGA system with OV5640 cameras
Hls_fpga_nes
⭐
14
An FPGA NES emulator designed by a high level synthesis (HLS)
Hog_zedboard
⭐
14
A real time Histogram of Oriented Gradients Implementation on FPGA
Rfnoc Hls Winlab
⭐
14
Hipacc Fpga
⭐
14
Fork of Hipacc generating code for Vivado HLS and Altera OpenCL
Xilinx_fpga_hls Mapping Neural Network To Hardware
⭐
14
At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA
Bnn
⭐
14
Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools
Solvercodegen
⭐
12
C++ code generation tools for real-time CPU or FPGA simulation solvers of electrical and power electronic systems
Pynq 2.7 Mnist
⭐
12
PYNQ-Based MNIST with Tensorflow Lite
Imagedetectionhw2
⭐
12
HOG + SVM on FPGA
Fpga_cpfp
⭐
12
HLS Custom-Precision Floating-Point Library
Finance.zynqpricer.hls
⭐
11
Heston implementation for Zynq with Vivado HLS
Sdsoc
⭐
11
SDSoC example projects
Digital Hardware Modelling
⭐
11
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
Stencilflow
⭐
11
C Ll Verilog
⭐
10
An LLVM based mini-C to Verilog High-level Synthesis tool
Comet
⭐
10
RISC-V ISA based 32-bit processor written in HLS
Mtcnn_with_hls_on_fpga
⭐
10
MTCNN with convolution reprogramed in c
Dach
⭐
9
DaCH: dataflow cache for high-level synthesis.
Memluv
⭐
9
An HLS-synthesizable Dynamic Memory Manager for FPGAs
Hls_ldpc_dec
⭐
9
Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..
Handwritten_mathematical_calculator_on_fpga
⭐
8
A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.
Ml Kws For Fpga
⭐
8
https://github.com/ARM-software/ML-KWS-for-MCU
Merlin Compiler
⭐
8
Falcon Merlin Compiler
Xf Fusion
⭐
8
提出了一种新的红外与可见光图像融合算法,并基于zynq搭建了图像融合应用。
Clink
⭐
8
Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.
Hls_for_cnn
⭐
7
This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.
Slam
⭐
7
SLAM dissertation project
Hls_blstm
⭐
7
The community version of HLS_BLSTM (A BLSTM FPGA accelerator of an OCR appilcation, using CAPI/SNAP))
Ece5775 Final
⭐
7
Voice Recognition using FPGA-Based Neural Networks
Reconfig
⭐
7
Implementation of various projects on Cyclone V FPGA
Leap Hls
⭐
7
Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework
Hls_arbitrary_precision_types
⭐
7
Jpeg_fpga
⭐
6
Implementation of JPEG Compression on an FPGA
Fpga Motion Detector
⭐
5
Motion detection in both software and in hardware-accelerated OpenCV
Lenet5 Accelerator
⭐
5
FPGA and GPU acceleration of LeNet5
Cnn_dpr
⭐
5
Landmark Detection with CNN on FPGA including DPR
Hls Zybo
⭐
5
A collection of HLS IP designs for Zybo-Z2
Visual System Integrator
⭐
5
Visual System Integrator - Accelerate your embedded development
Lofreq Fpga
⭐
5
FPGA Acceleration for the LoFreq variant caller
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