Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Openwifi | 3,363 | 4 months ago | 51 | agpl-3.0 | C | |||||
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software | ||||||||||
Basic_verilog | 1,333 | 4 months ago | Verilog | |||||||
Must-have verilog systemverilog modules | ||||||||||
Hls4ml | 1,084 | 10 days ago | 10 | November 16, 2023 | 164 | apache-2.0 | C++ | |||
Machine learning on FPGAs using HLS | ||||||||||
Pipecnn | 916 | 2 years ago | 35 | apache-2.0 | C | |||||
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks | ||||||||||
Nmigen | 589 | 2 years ago | 39 | other | Python | |||||
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen | ||||||||||
Openwifi Hw | 560 | 4 months ago | 5 | agpl-3.0 | Verilog | |||||
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware | ||||||||||
Fpga Network Stack | 559 | 7 months ago | 17 | bsd-3-clause | C++ | |||||
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2) | ||||||||||
Pipelinec | 519 | 3 months ago | 82 | gpl-3.0 | Python | |||||
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. | ||||||||||
Zynqnet | 510 | 7 years ago | 38 | gpl-3.0 | HTML | |||||
Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network" | ||||||||||
Pp4fpgas Cn | 394 | 2 years ago | 7 | CSS | ||||||
中文版 Parallel Programming for FPGAs |