Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
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Hw | 1,254 | 2 years ago | 193 | other | Verilog | |||||
RTL, Cmodel, and testbench for NVDLA | ||||||||||
Davos | 37 | 2 years ago | 4 | SystemVerilog | ||||||
Distributed Accelerator OS | ||||||||||
Hls Cnn | 19 | 4 months ago | mit | C | ||||||
High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition. | ||||||||||
Accsynt | 17 | 2 years ago | 1 | C++ | ||||||
Program synthesis tools and utilities for LLVM. | ||||||||||
Pymtl Tut Hls | 8 | 8 years ago | C++ | |||||||
Tutorial for integrating PyMTL and Vivado HLS | ||||||||||
Hls_for_cnn | 7 | 6 years ago | C | |||||||
This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera. | ||||||||||
Systems Lunch | 5 | a year ago | ||||||||
UMass CS Systems Lunch, organized by Emery Berger |