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A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

Bsv_tutorial_cn ⭐ 381

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开

Leechcore ⭐ 378

LeechCore - Physical Memory Acquisition Library & The LeechAgent Remote Memory Acquisition Agent

Parallella Hw ⭐ 377

Parallella board design files

Pynq Classification ⭐ 369

Python on Zynq FPGA for Convolutional Neural Networks

研究生阶段的一些文章（技术、思考、读书笔记、日常琐事等）

RISC-V CPU Core (RV32IM)

Nontrivial Mips ⭐ 362

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

Litedram ⭐ 341

Small footprint and configurable DRAM core

Openfpga Snes ⭐ 339

SNES for the Analogue Pocket

hBPF = eBPF in hardware

Deepfloat ⭐ 333

An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

Fpgadesignelements ⭐ 327

A self-contained online book containing a library of FPGA design modules and related coding/design guides.

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

PCB for ULX3S FPGA R&D board

Icesugar ⭐ 320

iCESugar FPGA Board (base on iCE40UP5k)

Vivado Boards ⭐ 312

Tillitis Key1 ⭐ 312

Board designs, FPGA verilog, firmware for TKey, the flexible and open USB security key 🔑

Upduino V3.0 ⭐ 306

UPduino 3.0: new 4 layer layout, various other improvements

Echomods ⭐ 305

Open source ultrasound processing modules and building blocks

Tinyfpga Bootloader ⭐ 304

An open source USB bootloader for FPGAs

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

Ov_ftdi ⭐ 303

FT2232H-based USB sniffer

Sdaccel_examples ⭐ 302

SDAccel Examples

Various HDL (Verilog) IP Cores

Biriscv ⭐ 300

32-bit Superscalar RISC-V CPU

Reduceron ⭐ 296

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to

Ua3reo Ddc Transceiver ⭐ 293

DDC/DUC SDR Tranceiver project

The original high performance and small footprint system-on-chip based on Migen™

Fpgatools ⭐ 291

public domain tools for FPGAs

Heterocl ⭐ 281

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing

Hastlayer Sdk ⭐ 281

Turning .NET software into FPGA hardware for faster execution and lower power usage.

Forth Cpu ⭐ 276

A Forth CPU and System on a Chip, based on the J1, written in VHDL

32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs

Limesdr Usb ⭐ 272

USB 3.0 version of the LimeSDR board

Fpga Imaging Library ⭐ 271

An open source library for image processing on FPGA.

Fpga Zynq ⭐ 268

Support for Rocket Chip on Zynq FPGAs

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

Plutosdr Fw ⭐ 262

PlutoSDR Firmware

Rapidwright ⭐ 262

Build Customized FPGA Implementations for Vivado

Code generation tool for configuration and status registers

Ustc Rvsoc ⭐ 261

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

Swapforth ⭐ 260

Swapforth is a cross-platform ANS Forth

A huge VHDL library for FPGA development

Nuked Md Fpga ⭐ 259

Mega Drive/Genesis core written in Verilog

Hdlconvertor ⭐ 258

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

Bladerf Wiphy ⭐ 255

bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

Hls4ml Tutorial ⭐ 253

Tutorial notebooks for hls4ml

Openofdm ⭐ 251

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

Fpga_readings ⭐ 249

Recipe for FPGA cooking

F4pga Arch Defs ⭐ 248

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Nestang ⭐ 245

NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards

Blueoil ⭐ 243

Bring Deep Learning to small devices

Verilog ⭐ 243

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Fpga Usb Device ⭐ 241

An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个

C64 Video Enhancement ⭐ 239

Component video modification for the C64 8-bit computer

Mipi_csi_receiver_fpga ⭐ 239

MIPI CSI-2 Camera Sensor Receiver verilog HDL implementation For any generic FPGA. Tested with IMX219 on Lattice MachXO3LF. 2Gbps UVC Video Stream Over USB 3.0 with Cypress FX3. This is now Legacy Version!

Introtospartanfpgabook ⭐ 239

A book on using the Spartan 3E FPGA with VHDL, using the Papilio One or Digilent Basys2 boards

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Wbuart32 ⭐ 237

A simple, basic, formally verified UART controller

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

Awesome Latticefpgas ⭐ 236

📖 List of FPGA Lattice boards using open tools

F4pga Examples ⭐ 232

Example designs showing different ways to use F4PGA toolchains.

Mega65 Core ⭐ 232

MEGA65 FPGA core

Fpga Litecoin Miner ⭐ 231

A litecoin scrypt miner implemented with FPGA on-chip memory.

Verilog Generator Of Neural Net Digit Detector For Fpga ⭐ 231

Verilog Generator of Neural Net Digit Detector for FPGA

Binary files for MiSTerFPGA, Pocket and other platforms

Opl3_fpga ⭐ 225

Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer

Ice40 Playground ⭐ 224

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

80186 compatible SystemVerilog CPU core and FPGA reference design

Cores Veer El2 ⭐ 222

Tinyfpga Bx ⭐ 218

Open source machine learning accelerators

Bnn Fpga ⭐ 218

Binarized Convolutional Neural Networks on Software-Programmable FPGAs

Fletcher ⭐ 217

Fletcher: A framework to integrate FPGA accelerators with Apache Arrow

Ip Cores ⭐ 214

A huge collection of VHDL/Verilog open-source IP cores scraped from the web

Nitefury And Litefury ⭐ 212

Public repository for Litefury & Nitefury

Systemrdl Compiler ⭐ 212

SystemRDL 2.0 language compiler front-end

Chips 2.0 ⭐ 205

FPGA Design Suite based on C to Verilog design flow.

Riscboy ⭐ 204

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

Vhdl_lib ⭐ 199

Library of VHDL components that are useful in larger designs.

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Colorlight Fpga Projects ⭐ 196

current focus on Colorlight i5 and i9 & i9plus module

Dblclockfft ⭐ 195

A configurable C++ generator of pipelined Verilog FFT cores

Jtcores ⭐ 194

FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket

Xilinx_axidma ⭐ 194

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

The USRP™ Hardware Driver FPGA Repository

Panda Bambu ⭐ 192

PandA-bambu public repository

Litex Buildenv ⭐ 191

An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Liteeth ⭐ 187

Small footprint and configurable Ethernet core

Convolution_network_on_fpga ⭐ 187

CNN acceleration on virtex-7 FPGA with verilog HDL

An open source SPI flash emulator and monitor

Gemm_hls ⭐ 184

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

💻 A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

Fpga Ftdi245fifo ⭐ 178

FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

the Open Vision Computer

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