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Search results for verilog

2,185 search results found

Iob Cache ⭐ 134

Verilog Configurable Cache

Minimig Aga_mister ⭐ 133

Macroplacement ⭐ 133

Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source

Zynq7010_eink_controller ⭐ 133

这是一个基于Zynq7010的Eink控制器在ED097TC2上高质量显示帧数高达10FPS

Sdram Controller ⭐ 131

Verilog SDRAM memory controller

Iob Soc ⭐ 131

RISC-V System on Chip Template

Usb_cdc ⭐ 131

Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs

Caravel_mpw One ⭐ 130

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

Tekno Kizil ⭐ 129

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

Neogeo_mister ⭐ 128

NeoGeo for MiSTer

Usb3_pipe ⭐ 126

USB3 PIPE interface for Xilinx 7-Series

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

A Video display simulator

Image Processing ⭐ 123

Image Processing Toolbox in Verilog using Basys3 FPGA

Milkymist ⭐ 123

SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU

Corescore ⭐ 122

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

32 Verilog Mini Projects ⭐ 121

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SP

Vsdflow ⭐ 121

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Ope

Fpga Can ⭐ 121

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

Hardcaml ⭐ 120

[Deprecated see github.com/janestreet/hardcaml] Register Transfer Level Hardware Design in OCaml

Dspfilters ⭐ 119

A collection of demonstration digital filters

Learning Nvdla Notes ⭐ 117

NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]

Ice40_ultraplus_examples ⭐ 115

Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

Dreamcasthdmi ⭐ 115

Digital Ide ⭐ 114

all in one vscode plugin for Verilog/VHDL development

Cocotb Test ⭐ 114

Unit testing for cocotb

SystemVerilog support for Yosys

Tinygarble ⭐ 113

TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits

Genesis_mister ⭐ 113

Sega Genesis for MiSTer

Fpga_based_cnn ⭐ 113

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

Emulate Integrated Circuits at the logic level

Istyle Verilog Formatter ⭐ 112

Open source implementation of a Verilog formatter

FM sound source written in Verilog, fully compatible with YM2612, YM3438 (JT12), YM2203 (JT03) and YM2610 (JT10)

Simplevout ⭐ 112

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

Tinytpu ⭐ 111

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

A Verilog implementation of the Infocom Z-Machine V3. With BIOS and benchmarks. Verified in hardware.

SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA

Cnn Fpga ⭐ 109

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

Simple 3-stage pipeline RISC-V processor

Ultimatecart ⭐ 108

SD-card multicart for Atari 8-bit computers

http://openasic.org/

Icesugar Pro ⭐ 107

iCESugar series FPGA dev board

Haasoscope ⭐ 107

Docs, design, firmware, and software for the Haasoscope

Aib Phy Hardware ⭐ 107

Advanced Interface Bus (AIB) die-to-die hardware open source

Icestation 32 ⭐ 107

Compact FPGA game console

Schoolmips ⭐ 106

CPU microarchitecture, step by step

Fpga_pio ⭐ 106

An attempt to recreate the RP2040 PIO in an FPGA

MCPU - A Minimal 8Bit CPU in a 32 Macrocell CPLD

SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" <https://people.inf.ethz.ch/omutlu/pub/softMC_hpca

Tang_e203_mini ⭐ 103

LicheeTang 蜂鸟E203 Core

Benchmarks ⭐ 102

EPFL logic synthesis benchmarks

C64_mister ⭐ 102

Opene906 ⭐ 102

OpenXuantie - OpenE906 Core

A complete open-source design-for-testing (DFT) Solution

Standard Cell Library based Memory Compiler using FF/Latch cells

Dinocpu ⭐ 101

A teaching-focused RISC-V CPU design used at UC Davis

Verilog Perl ⭐ 101

Verilog parser, preprocessor, and related tools for the Verilog-Perl package

Ice Chips Verilog ⭐ 99

IceChips is a library of all common discrete logic devices in Verilog

Openlane2 ⭐ 99

The next generation of OpenLane, rewritten from scratch with a modular architecture

Spatial Lang ⭐ 98

Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"

Mobilenet In Fpga ⭐ 96

Generator of verilog description for FPGA MobileNet implementation

Fpga Application Development And Simulation ⭐ 96

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

Panologic G2 ⭐ 96

Pano Logic G2 Reverse Engineering Project

Openfgpa Gbc ⭐ 96

Universal Memory Interface (UMI)

Regression test suite for Icarus Verilog. (OBSOLETE)

A Scannerless GLR parser/parser generater.

A 32-bit Microcontroller featuring a RISC-V core

Fft Dit Fpga ⭐ 94

Verilog module for calculation of FFT.

Ice40_examples ⭐ 94

Public examples of ICE40 HX8K examples using Icestorm

Verilog Lfsr ⭐ 92

Fully parametrizable combinatorial parallel LFSR/CRC module

Gameboy_mister ⭐ 91

Gameboy for MiSTer

SD-Card controller, using a SPI interface that is (optionally) shared

Bazel_rules_hdl ⭐ 90

Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

Opencgra ⭐ 90

OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.

Verismith ⭐ 89

Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

Vlsiffra ⭐ 89

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

Oldland Cpu ⭐ 89

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

Veridian ⭐ 88

A SystemVerilog Language Server

Displayport_verilog ⭐ 88

A Verilog implementation of DisplayPort protocol for FPGAs

Pipelinec Graphics ⭐ 88

Attempt to verilog Implementation of Playstation 1 (PSX) chips.

Opene902 ⭐ 88

OpenXuantie - OpenE902 Core

Kamikaze ⭐ 88

Light-weight RISC-V RV32IMC microcontroller core.

Apple One ⭐ 87

An attempt at a small Verilog implementation of the original Apple 1 on an FPGA

Neogeofpga Sim ⭐ 87

Simulation only cartridge NeoGeo hardware definition

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

100 Days Of Rtl ⭐ 87

The Task Parallel System Composer (TaPaSCo)

Agc_simulation ⭐ 86

Verilog simulation files for a replica of the Apollo Guidance Computer

Haskell library for hardware description

Colorlight Led Cube ⭐ 86

64x64 LED Cube based on the Colorlight 5a-75B LED driver board.

2 hour crash course in FPGAs

Hardware definition language that compiles to Verilog

Lispmicrocontroller ⭐ 85

A microcontroller that natively executes a simple LISP dialect

The Shang high-level synthesis framework

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