C64_mister
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Ustc Rvsoc | 261 | 7 months ago | 4 | gpl-3.0 | SystemVerilog | |||||
| An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。 | ||||||||||
| Ao486_mister | 223 | 5 months ago | 46 | other | Verilog | |||||
| ao486 port for MiSTer | ||||||||||
| Neogeo_mister | 128 | 5 months ago | 4 | gpl-2.0 | Verilog | |||||
| NeoGeo for MiSTer | ||||||||||
| C64_mister | 102 | 4 months ago | 33 | Verilog | ||||||
| Gameboy_mister | 91 | 5 months ago | 4 | Verilog | ||||||
| Gameboy for MiSTer | ||||||||||
| Neogeofpga Sim | 87 | 3 years ago | gpl-3.0 | Verilog | ||||||
| Simulation only cartridge NeoGeo hardware definition | ||||||||||
| Vt52 Fpga | 83 | 3 years ago | 2 | gpl-3.0 | Verilog | |||||
| Cscvon8 | 58 | 4 years ago | gpl-3.0 | Perl | ||||||
| A crazy small 8-bit CPU built with only seventeen 7400-series chips. | ||||||||||
| Spam 1 | 53 | 8 months ago | 1 | mpl-2.0 | Verilog | |||||
| Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu | ||||||||||
| Up5k_basic | 50 | 5 years ago | mit | Verilog | ||||||
| A small 6502 system with MS BASIC in ROM | ||||||||||
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